After looking into the data, which is seen by the FPGA. We noticed, that the Jetson module is sending the PCIe compliance pattern for 8b/10b.
What could be the reason for this? Is there some entry in the device tree, which could lead to such a behavior? Or some levels on some pins of the module?
Is it possible to readout via register, if the PCIe complex of the Jetson module is sending out the compliance pattern?