PCIe Device - No Link

[cioma]

Generally speaking the best sequence would probably be as follows:

1. On power on and hardware reset: VDD_12V is disabled, PCIE_REFCLK_P/N is disabled, PEX_L5_RST_N_R is active (low)

2. Perform other boot activities as required keeping signals as previously described. Also guarantee it takes at least 100 ms to allow capacitance discharge in case of hardware reset

3. Enable VDD_12V and wait for it to stabilize

4. Enable PCIE_REFCLK_P/N and wait for it to stabilize

5. Wait 100 ms

6. Make PEX_L5_RST_N_R inactive (high)

7. Check for PCIe link multiple times with timeout (e.g. 100 ms)

If PCIe link is not up:

8. Make PEX_L5_RST_N_R active (low) with delay after it

9. Disable PCIE_REFCLK_P/N with delay after it

10. Disable VDD_12V with delay after it

[vidyas]

Can you please check the behavior with the below patch?
Please also capture signals if possible.

diff --git a/drivers/pci/host/pcie-tegra-dw.c b/drivers/pci/host/pcie-tegra-dw.c
index 63ec46b3430b..f90a801a7463 100644
--- a/drivers/pci/host/pcie-tegra-dw.c
+++ b/drivers/pci/host/pcie-tegra-dw.c
@@ -3106,7 +3106,7 @@ static int tegra_pcie_dw_runtime_resume(struct device *dev)
                }
        }
 
-       config_plat_gpio(pcie, 1);
+       //config_plat_gpio(pcie, 1);
 
        ret = regulator_enable(pcie->pex_ctl_reg);
        if (ret < 0) {

[bruce.ashford]

@vidyas: I’m just following up on earlier posts from my colleagues @cioma and @c_seymour. Thanks for your suggestions for changes to the PCIE driver code. I have been working on applying these.

We have three Jetson Xavier development units. On the first, we have added the patches for the 5s delay in tegra_pcie_dw_host_init() and disabled the call to config_plat_gpio() in tegra_pcie_dw_runtime_suspend().

On the second, we have again added the 5s delay but this time disabled the calls to config_plat_gpio() in tegra_pcie_dw_runtime_resume().

On the third, we have added the 5s delay and disabled the calls to config_plat_gpio() in both tegra_pcie_dw_runtime_resume() and tegra_pcie_dw_runtime_suspend().

Unfortunately, the PCIE card is still not being initialised by any of the units but my colleagues are working to get some traces from the bus and we will post those shortly.

NB: I noticed that drivers/pci/host/pcie-tegra-dw.c no longer gets compiled into the kernel. It appears that these functions are now present in drivers/pci/dwc/pcie-tegra.c so I have applied your suggestions here instead and verified from dmesg that this is the code being run.

[cioma]

It seems that keeping VDD_12V enabled gives the correct PCIe signal sequence on power-on but still no link. We’ll see how we can debug it from the FPGA side.

[lemon_tea]

Hi，
I think we also have the same issue with PCIe, is this problem fixed ?

[lemon_tea]

Great, we’re using Si53102-A3 clock buffer on the board c_seymour is bringing up so a DC-coupled LVDS input clock shall be fine for it.

I monitored PEX_CLK5_P signal and I’ve noticed that this PCIe clock is briefly enabled on power-on/reset, then disabled while OS boots, then enabled for about 2 ms at some stage of the boot process and then disabled again (presumably because it doesn’t detect PCIe link). Does this 2 ms PCIe clock enable period corresponds to anything in the code?

Hi, any solution for this issue ? I think we have the same problem.

[ahepner]

@vidyas

Is there a way to keep VDD_12V power rail (which powers PCIe x16 slot) enabled even if OS doesn’t detect PCIe link?

Following patch can be used to keep 12V slot power flowing to slot even if PCIe link is not up

diff --git a/drivers/pci/host/pcie-tegra-dw.c b/drivers/pci/host/pcie-tegra-dw.c
index 63ec46b3430b..6e2ea926d4e9 100644
--- a/drivers/pci/host/pcie-tegra-dw.c
+++ b/drivers/pci/host/pcie-tegra-dw.c
@@ -3082,7 +3082,7 @@ static int tegra_pcie_dw_runtime_suspend(struct device *dev)
        reset_control_assert(pcie->core_apb_rst);
        clk_disable_unprepare(pcie->core_clk);
        regulator_disable(pcie->pex_ctl_reg);
-       config_plat_gpio(pcie, 0);
+       //config_plat_gpio(pcie, 0);

        if (pcie->cid != CTRL_5)
                uphy_bpmp_pcie_controller_state_set(pcie->cid, false);

i can confirm this hack works to keep VDD on, keep in mind asTHE SOURCE FILE IS WRONG!!!

as mentioned by @bruce.ashford, “/drivers/pci/host/pcie-tegra-dw.c” does not compile to the kernel

you should edit “/drivers/pci/dwc/pcie-tegra.c” which implements the same functions.

next we should find out how to control power from user space and re-initiate probing.

my personal lesson is to read the entire post

[enarasanz4]

where and how does this change have to be done? I have a similar situation, FPGA connected through the PCI port to jetson Xavier and same messages but I can’t find the file pcie-tegra-dw.c to make the changes.

[kayccc]

Hi enarasanz4,

Please help to open a new topic for your issue with more details. Thanks