PCIe direct write to frame buffer

I am using a PCIe FPGA to write directly to the video display on an old GeForce card. Using a PCIe protocol analyzer I can see CPU driven memory writes to the memory range specified by fbset (at 0xe000f000). However when my FPGA writes into the same address range, I see some pixels updated based on my PCIe memory write, but there is a lot of other PCIe activity that may be related to screen re-draws, etc.

Is there a way I can perhaps turn off the Nvidia smarts to allow access of a non-driver PCIe device write access to the frame buffer?


Hi, just a followup based on scanning other forum discussions that may relate to this topic. I am certainly aware of the issues surrounding memory coherency and multiple writer issues. This is a research topic where I am trying to determine how much latency (mainly through TCP/IP stack) and CPU cycle overhead (and popwer) compares to a NIC FPGA writing directly to a video frame buffer. Consider the case where a tablet is streaming video, during much of playtime, the CPU could grant memory write permission to the NIC to directly write to the frame buffer. On buffer under-runs, or user interaction the CPU would certainly regain conventional control and communication.

Ideally I would like to write an H.264 stream directly to the Nvidia device, so any pointers/examples on this or basic frame access writes are appreciated.

Maybe the Data Transfer Matters for GPU Computing paper has some interesting pointers for you. You can find the used source code at https://github.com/shinpei0208/gdev.