pcie endpoint dma interrupt doesn't make effect

Autonomous Machines Jetson & Embedded Systems Jetson AGX Xavier
1

RC configures EP DMA and DMA is successful. I remove dma done interrupt mask and enable LIE(local interrupt enable) in control register, but the process doesn’t enter tegra_pcie_irq_handler. How can i enable DMA local interrupt in endpoint? thanks

2

What is the meaning of endpoint dma local interrupt? Can the pcie endpoint recieve dma interrupt configured by pcie host? thanks

3

Is there any document for it?

4

Each DMA channel can be used by either the system containing the DMA controller, or (when Jetson is a PCIe endpoint) by the system that is the PCIe host/root-port. LIE (“Local Interrupt Enable”) enables generating interrupts to the CPU of the system that contains the DMA controller. RIE (“Remove Interrupt Enable”) enables generating interrupts from a PCIe EP system to the host/root-port system.

I am not exceedingly familiar with the DMA HW. However, I think/suspect that LIE/RIE (in the DMA transfer configuration registers or a descriptor in the linked list) values are only consulted at the time a DMA transfer completes. It sounds like you’re letting the DMA transfer complete, then setting the LIE bit. Please try setting LIE as part of the initial DMA transfer request. I believe Mask/Status registers apply immediately though; I think it’s just the “generate an interrupt” action that is a one-time thing.

There is some documentation of the DMA controllers in the Xavier TRM. I am told that the following series of kernel patches is for the same HW that’s in Jetson Xavier, so there may be relevant information there:
https://patchwork.kernel.org/project/linux-pci/list/?series=109193

5

Hi,

Enable INT_INT_EN bit in PCIE_RP_APPL_INTR_EN_L0_0 and EDMA_INT_EN bit in PCIE_RP_APPL_INTR_EN_L1_8_0 to enable EDMA interrupt. Then we get tegra_pcie_ep_irq_handler() with INT_INT bit set in PCIE_RP_APPL_INTR_STATUS_L0_0, and inside INT_INT status, driver has to check for EDMA_INT in PCIE_RP_APPL_INTR_STATUS_L1_8_0. Refer to “PCIe Root Port” section in TRM for details of these registers.

After getting this interrupt you have check for DMA channel specific register to find out for on which channel & direction you got interrupt. Refer to “PCIe IATU” section for this information.

Manikanta