The pinmux file looks correct.
I’m already use Sperated Reference No spread Clock.
Please compare the C7 ep node with C5 ep node and see if any missing field.
Then I think software has nothing to configure. Please attach full schematic for this part to review.
We have a NVIDIA F110 PCIe AccleratorCard, it uses Jetson AGX Xavier PCIe Endpoint Software for L4T BSP R35.5.0. We follow the steps of "Connecting and Configuring the Devices" in this link: https://docs.nvidia.com/jetson/archives/r36.3/DeveloperGuide/SD/Communications/PcieEndpointMode.html?highlight=endpoint, to type the commands.
At the last step which is after “echo 1 > controllers/141e0000.pcie-ep/start”, must reboot the pcie rp board. Why need to reboot? Has any method that while the system boots, the pcie ep board can automatically connect to pcie rp board without manually typing any command and without rebooting the system?
I have attached the circuit diagram below.
EIP_MAIN_REV_3A_OCULINK_02Sep.pdf (134.9 KB)
EP and RP board connect with OCulink cable
There is only connector in your shared schematic. I don’t see isolator and others like the Connection Example in DG. Please follow the Design Guide to make your custom design first and then ask for help of SW.
I did not use the ISOLATOR because I am using two custom boards, one set to EP mode and the other set to RP mode. The EP board and the RP board are connected via CON2900 (OcuLink connector) in the schematic.
Your design is different to reference and its feature can not be guaranteed.
As said, your design is different to reference. There is no isolator b/w RP and EP in your design which might cause issue. Please follow the Design Guide to change your custom design first and then ask for help of SW.
Yes, that is necessary.
I have a question.
Looking at the block diagram on the DG below, there is a line called “EP_READY_N” connected to GPIO38,
but on the AGX ORIN EVB circuit diagram, “ETH_WOL_EN_STATUS” is connected, and there is no definition(GPIO38) on the device tree. Is this a necessary pin for PCIe EP/RP operation?
My custom board does not have the “CLKREQ N” line connected as shown in the block diagram below. I am using SRNS, do I still need the CLKREQ_N line?
Please refer to Table 7-18. PCIe Signal Connections AGX Orin RP to AGX Orin EP for each pin usage. EP_READY_N should be used. CLKREQ_N could be unused if it is SRNS, but still better to have the design as backup option especially for the first build.
You said that EP_READY_N is needed, but I can’t find the part in dts that defines EP_READY_N(GPIO)? Can you tell me where I should modify it?
The default dts is for devkit and so has no EP_READY_N. It is GPIO38 as you can see in DG. You should use it in your custom dts settings.
There is no example, I don’t know how to map EP_READY_N in pcie/pcie-ep driver.
Can you provide an example code?