PCIe Interface Signal Routing Requirements according to Orin Nano Series Design Guide V1.3

Robotics & Edge Computing Jetson & Embedded Systems Jetson Orin Nano
1

Hello,

in table 7-10. It is recommended to use micro vias or back drilled vias and additionally there are only 4 vias allowed. Regarding the connector it is recommended to void ALL layers under gold finger pads.
Are those constraints really necessary for PCIE Gen3?

Regards,
Sven

3

That’s for up to Gen4. For Gen3 only, you can refer to the spec in Xavier NX DG. Jetson Xavier NX Product Design Guide

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