PCIe lane mapping issue for CONFIG#3

Hi,

I am making lane mapping changes as mentioned in the platform adaptation guide for config#3
I always see the following error message in dmesg
Tegra PCIe IDDQ error: wrong lane config

And I am not able to see any devices under lspci
As i was going through datasheet, i came across step 16 of root port initialization
Set Lane IDDQ and SLEEP Override

So my question is that, is it that due above error(as shown in dmesg) the IDDQ lane setting has failed and that is the cause of pci not getting initialized correctly?
Is my understanding correct? could someone clarify why is shows wrong lane config error as it is the valid configuration?
Also is there any document explaining PCIe in Tx1 in details, details about PCIe in Tx1 are somewhat vague and not clear.

Thanks,
Prathamesh

Hi patyarahate, please refer to
http://developer.nvidia.com/embedded/dlc/jetson-tx1-oem-product-design-guide

Hi Dane,

Thanks for the reply.
I have already gone through those docs and reached this far. But i feel they are not sufficient.
I tried to trace error and it lead me to following function and after manually setting lane_owner i could get rid of the error.
Not sure why its not picked up from device tree. following are the changes
[b]— a/drivers/platform/tegra/tegra_usb_pad_ctrl.c
+++ b/drivers/platform/tegra/tegra_usb_pad_ctrl.c
@@ -1960,6 +1960,7 @@ static int tegra_pcie_lane_iddq(bool enable, int lane_owner)
#endif

    val = readl(pad_base + XUSB_PADCTL_USB3_PAD_MUX_0);
  •   lane_owner = 0x12;
      switch (lane_owner) {
    

#ifdef CONFIG_ARCH_TEGRA_21x_SOC
case PCIE_LANES_X4_X1:
@@ -2211,6 +2212,7 @@ int pcie_phy_pad_enable(bool enable, int lane_owner)
tegra_pcie_lane_misc_pad_override(true, lane_owner);

    val = readl(pad_base + XUSB_PADCTL_USB3_PAD_MUX_0);
  •   lane_owner = 0x12;
      switch (lane_owner) {
    

#ifdef CONFIG_ARCH_TEGRA_21x_SOC
case PCIE_LANES_X4_X1:
[/b]

But even above thing did not solve the issue.
Thanks,
Prathamesh

Hi patyarahate,
Are you on r28.1 or r24.2.1? The programming of device tree is very different between the two BSP releases.

Hi Dane,

I am on r24.2.1
After spending sometime I could get some understanding of lane mapping.
So I have custom board and I am using lane 4 for PEX0/PCIE0 for x1 PCIE device.
And combining USB2_port0 with USBSS0(lane5) for USB3.0 port.
So following is the lane configuration I have done,

lane-map=0x14
ss_portmap=0x7707
lane_owner=0xff56

Is my configuration correct?

Thanks,
Prathamesh

Hi patyarahate,
The configuration is not right. Please refer to R24 Example 1.
you should disable PCIe#1_0 and enable USB_SS#2 in lane 0.