PCIe link discovery

Attempting to link FPGA-based pcie endpoint on custom hardware to Xavier (L4T32.1)

Something is keeping the 12V from coming up when connected to our board.

Have tested endpoints on two working reference designs and I have verified the following…
-CLKREQ is not needed (NC on one reference design)
-PERST and WAKE come up after 12V and 3V3
-PRSNT#1/#2 is not monitored by xavier (concept schematic shows no connection)

What verifies an enpoint is plugged in?
What tells it to bring up the 12V supply?

Thank you for help on any clarification.
pcie_mrb_full.log (71 KB)
pcie_mrb_grep.log (7.67 KB)

I’m not sure about the schematics received by you but 12V is dependent on PRSNT also. You can short them to Ground (to enable 12V) for debugging purposes.
There are GPIO controls also present to enable 12V, but those are handled by the host controller driver.
Also, please note that, if the PCIe link doesn’t come up with the endpoint, then, host controller driver disables these GPIOs so 12V won’t be present later on.

Using schematic from design files ending in *_B03
Concept sch shows PEX_PRSNT_L connected to a DNS MOSFET(Q87) but no where else.
Orcad sch shows Q87 present.
I’ve looked on the board and Q87 is not there.

On my hardware I have jumpered A1(GND) to B31(PEX_PRSNT_L), 12V doesn’t attempt to come up.

If this is true, I shouldn’t have 12V come up on working reference designs, right?

I’m having trouble getting clarity on this.

You can trace the line “12V_SYS_EN” and it is controlled by “GPIO05_VDD_12V_ENABLE” also.
“12V_SYS_EN” finally goes to U9 which is an OnSemi’s buck boost regulator.
“GPIO05_VDD_12V_ENABLE” finally goes to Tegra’s GPIO (A, 1). This needs to be configured as an active-low GPIO.
You can find corresponding entries in the DT and GPIO configuring code in the driver (pcie-tegra.c) also.