Hi,
Currently we are having a setup like one jetson xavier acts as RC and another jetson xavior acts as Endpoint.
I could able to see End point is detected in RC and also accessed the end point memory from RC using devmem commands.
But when i checked the link status from register PCIE_X4_RC_PF0_PCIE_CAP_LINK_CONTROL_LINK_STATUS_REG_0 (0x3a000080), i observed link is not established at GEN4. It was established in gen1, Even though in device tree we have the following entry
nvidia,max-speed = <0x00000004>;
Further when i try to change the speed by updating target_speed and apply_speed_change fields in debugfs interface, link speed changes successfully for only Gen1 and Gen2. It fails for Gen3 and Gen4.