PCIE Logic Level IO Standard for PCIE0 on M.2 Key M connector of Jetson NX

Autonomous Machines Jetson & Embedded Systems Jetson Xavier NX
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1

Hi,

In our application, we are using PCIE0 port on M.2 Key M connector (J11) of NVIDIA Jetson NX board as Root Complex port,

We need to confirm the what is Logic level IO standard used for the PCIE0 port, i.e., CML, LVPECL, LVDS etc.

We have gone through the design guide and all other design related document for the Jetson NX board, but couldn’t able to find the above information.

Please share the Logic level IO standard details for the PCIE port 0 of Jetson NX board.

Regards,
Harsh

3

You can refer to this topic: Regarding PCIE clock of Jetson TX2 - #5 by vidyas

4

Thanks for your reply.

Yes, As per design guide of Jetson Xavier NX, PCIE REFCLK supports “HCSL” IO logic level standard.

Reference: Jetson_Xavier_NX_Product_Design_Guide_DG-09693-001_v1.3.
Page number: 35, Figure 6-8. PCIe Root Port Connections Example.

But, my query is What type of logic level differential IO standard (CML, HVDS, LVPECL or any other) support for the PCIE data Tx and Rx lanes?

DG mentioned only about AC coupling capacitors on Tx port, while AC Cap on Rx port on connector board connected on M.2 Key M (J11).

There were no mentioned about the type of IO standard and termination scheme need to follow for data lanes, please suggest for the same.

Thanks,
Harsh

5

Hi, checked internally, Tegra PCIe supports HCSL IO spec.

6

Please confirm, Rx/Tx data lanes are internally (inside Tegra SoC chipset) ground terminated with 50E for “HCSL” differential IO standard.

Thanks.
Harsh

7

Yes, it supports HCSL IO spec.

8

Very much thanks for your input.

However, we have a concern about Logic level IO standard compatibility between PCIe repeater and Nvidia Jetson.

We are working on Proof of Concept development project, where below sub-systems are connected:

  1. End Point: Arria 10 SX development Kit (Intel® Arria® 10 SX SoC Development Kit)
  2. Repeater: DS125BR401SQE (DS125BR401 data sheet, product information and support | TI.com)
  3. Root Complex: Nvidia Jetson Xavier NX development kit (Jetson Xavier NX Developer Kit | NVIDIA Developer)

I have attached, overall system diagram about PCIe connections between RC and EP.
System logic IO standard compatibility.pdf (85.9 KB)

In-between those boards, we have used PCIe repeater IC, because PCIe signals have ~15 inch cable/traces to travel between RC and EP.

Repeater IC supports CML compatible inputs and outputs, to support CML compatible output to EP (Jetson NX), EP should have termination at it’s receiver port (you have mentioned previously that Jetson support HCSL IO spec.).

As, we have very limited space in our boards, so may be we can’t provide external termination for the PCIE0 port of Nvidia Jetson NX to make HCSL compatible with CML IO of repeater.

So, kindly confirm that PCIE0 Rx/Tx data lanes port of Jetson NX have internally terminated pull-up and Pull-down which is have HCSL IO spec compatibility, also is it configurable and have multiple termination resistor choices?

Regards,
Harsh

9

It is 50ohm single ended as you can see in the product design guide in DLC.

10

Many thanks for your response.

As there are multiple documents available in the shared folder: Jetson Download Center | NVIDIA Developer.

However, I have checked document: https://developer.nvidia.com/jetson-xavier-nx-product-design-guide, but couldn’t able to find mentioned details about HCSL (50 Ohm termination).

Could you please share exact document link for the same?

Regards,
Harsh Bhuva

11

No doc for HCSL info currently, it is from internal checking. The 50ohm termination is listed in the table of PCIe Interface Signal Routing Requirements in design guide.

13

Thanks for information and prompt replies.

14

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