Very much thanks for your input.
However, we have a concern about Logic level IO standard compatibility between PCIe repeater and Nvidia Jetson.
We are working on Proof of Concept development project, where below sub-systems are connected:
- End Point: Arria 10 SX development Kit (Intel® Arria® 10 SX SoC Development Kit)
- Repeater: DS125BR401SQE (DS125BR401 data sheet, product information and support | TI.com)
- Root Complex: Nvidia Jetson Xavier NX development kit (Jetson Xavier NX Developer Kit | NVIDIA Developer)
I have attached, overall system diagram about PCIe connections between RC and EP.
System logic IO standard compatibility.pdf (85.9 KB)
In-between those boards, we have used PCIe repeater IC, because PCIe signals have ~15 inch cable/traces to travel between RC and EP.
Repeater IC supports CML compatible inputs and outputs, to support CML compatible output to EP (Jetson NX), EP should have termination at it’s receiver port (you have mentioned previously that Jetson support HCSL IO spec.).
As, we have very limited space in our boards, so may be we can’t provide external termination for the PCIE0 port of Nvidia Jetson NX to make HCSL compatible with CML IO of repeater.
So, kindly confirm that PCIE0 Rx/Tx data lanes port of Jetson NX have internally terminated pull-up and Pull-down which is have HCSL IO spec compatibility, also is it configurable and have multiple termination resistor choices?