Hello and regarding,
What are the steps to change the PCIE_REFCLK_SEL value connected to PCIe clock reference MUX so that the AGX Orin developer kit would receive the reference clock from the endpoint device?
the device connected is a Polarfire SoC FPGA (VideoKit Eval board) configured as endpoint but the clock on the FPGA board does not have a switch so the only logical solution is to provide the clock from the endpoint side.
Please let me know if there are better soloutions.