I found the pcie programming guidelines chapter in Xavier TRM DP09253002.
How can I get the register information about
such as CLK_RST_CONTROLLER_RST_DEV_UPHY_0[SWR_UPHY_RST] or
CLK_RST_CONTROLLER_RST_DEV_PEX_USB_UPHY_0[SWR_PEX_USB_UPHY_RST] which are refered in the document.
May I know why you need those info? What’s your use case?
I’d like to setup Javier AGX devkit PCIe(EP) in ATF bl32. I have tried with BPMP API and it does’t work. ATF bl32 hangs when read or write pcie base address. But it works in Cboot. ATF bl32 run in EL3/Secure and Cboot run in EL2/ NS.
Need to do something in MB1 BCT?
I have one more question.
I wonder the SMLH_LTSSM_STATE encoding value which is PCIE_RP_APPL_DEBUG_0[8:3] I saw in Xaveir TRM document.
This is not a supported use case.
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