We are using Jetson Orin NX with JetPack 6.2.2. Our design includes an M.2 M-key slot that supports both USB and PCIe devices. The RST pin on this slot is connected to the PCIe bus reset signal.
We have encountered a problem: when a USB device is plugged in, there is no PCIe device present on the bus, so the PCIe driver pulls the RST pin low. This prevents the USB device from working properly because the RST pin is shared.
To work around this, we changed the pinmux configuration of the RST pin to GPIO mode and drove it high. This allows USB devices to function correctly. However, when we later want to use a PCIe device, we lose the ability to control the RST pin through the PCIe controller, which causes issues during PCIe device initialization.
We are wondering if there is any proper method or device tree property that can accommodate this kind of mixed-use design (USB and PCIe sharing the same M.2 slot).
We recall that older L4T versions had properties like nvidia,enable-power-down or nvidia,disable-power-down that might have helped control this behavior. Does JP 6.2.2 provide any similar mechanism to achieve this?
Sharing a PCIe reset line with a USB controller through pinmux is a common carrier-board trap. The cleanest path depends on whether the slot is truly “either/or” or whether you can detect the inserted device type at runtime.
If the slot is either PCIe or USB (one device type per boot):
- Keep the reset pin under PCIe controller ownership in the device tree, but add a reset-gpios property to the PCIe node only if the controller supports GPIO reset mapping.
- For USB mode, use a separate device-tree overlay that reassigns the pin to GPIO and leaves PCIe disabled. Switch overlays at boot based on the installed module.
If you need hot / runtime switching:
- You will need a mux/level-shifter with an enable controlled by a GPIO, plus a small platform driver or udev rule to toggle direction. This is not something the standard PCIe/USB controllers can coordinate for you.
- Make sure the reset pulse timing meets both PCIe (T_PERST# ≥ 100µs after power-good) and USB hub/controller requirements.
The Jetson AGX Orin / Orin NX pinmux spreadsheet and the L4T kernel source drivers/pci/controller/pcie-tegra194.c are the authoritative references. If you can share the exact pin name and the current DTS pcie node, I can suggest the exact pinmux and padctl changes.
Regarding the disable-power-down.diff patch you mentioned that is applicable to JP6, I’d like to ask: does this same patch also work for JP7.2 (rel-37/38)? Or is a different patch or method required?
I noticed in the Tuning Guide’s revision history that the disable-power-down.diff patch was specifically prepared for rel-36 (JP6), while 319ad28_ok.diff was for rel-35 (JP5). So I’m not sure if it can be directly applied to the newer JP7.2 version, and would like to confirm.
Thanks for the detailed analysis – appreciate the time you put into this.
That said, the approach you described seems quite complex for our needs. What we’re really trying to achieve is simple: keep the PCIe RST pin high when no PCIe device is present, while preserving full PCIe functionality.
We found the disable-power-down.diff patch in the Tuning Guide, which appears to do exactly that with minimal changes. We haven’t validated it on JP6.2.2 yet, but we’ll test it and report back the results.