I have been trying to implement PCIe communication between a Jetson TX2 and various endpoints, on a custom carrier board. I noticed that I cannot communicate successfully when REFCLK connection is not present. I can see the link is up, but EPs cannot be enumerated.
The errors are:
- PCIe AER System errors. Mostly Bad TLP and DLLP.
- Reading full ones as VendorID. I can see my host bridge controller, but in PCI scan functions inside kernel, vendorID is read as 0xFs. Also, I get AFI_INTR_MASTER_ABORT interrput.
All the errors above disappear with REFLCK connection. Also, I have seen there may be timing issues especially with FPGA EPs, but I verified that all my EPs wake up earlier than Jetson TX2.
I haven’t been able to see an exact statement that says TX2 does not support separate clock configuration for PCIe, but I saw this forum entry: https://devtalk.nvidia.com/default/topic/1067173/jetson-tk1/pcie-clock-synchronization-issue/
Does Jetson TX2 support separate clock configuration? If so, and since there seems to be no device tree interface for it, can you point me the right direction to implement the configuration myself?
Thanks in advance.