PCIE SI measurement

Autonomous Machines Jetson & Embedded Systems Jetson Nano
#1

Hi,
We are trying to measure PCIE signal and the signal doesn’t output.
From document: Jetson_Xavier_NX_Tuning_and_Compliance_Guide_Application_Note_DA-09890-001_v1.2, there’s a patch to enable PCIE root port always.
On Jetson Nano platform, the behavior is similar to Xavier: When there’s no device under PCIE root port, the root port is disabled.
However, we can’t find information to always enable root port for SI check in document: Jetson_Nano_Interface_Tuning_Complaince_Guide_Application_Note_v1.1.

Would you please teach us to enable the root port when no device connected?

Thanks.
Wayne

#7

Hi,
Any update for this question?
Thanks.
Wayne

#8

Hi Nvidia FAE,
I’m on the same team as Wayne.
Could you help us to update this question??

Thanks.
Ken

#9

I’m checking with team to know if there is such patch existed for Jetson Nano.

#10

Hi Kayccc,
Any update for this issue?
Thanks.

Wayne

#12

Hi,

Remove “nvidia,enable-power-down” property from all PCIe nodes and flash kernel DTB. Then you can see PCIe root port device in lspci output.

Thanks,
Manikanta

#13

Hi Manikanta,

We are using L4T 32.6.1 codebase . I searched all “Nano” PCIe node, there are not including “nvidia,enable-power-down” property in original codebase. But due to WiFi issue (Jetson Nano custom motherboard Wifi doesn't work) , we only modify PCIE node with remove the following property

/delete-property/ iommus;
/delete-property/ iommu-map;
/delete-property/ iommu-map-mask;

Have any idea about why we still see only one PCIe root port?

00:02.0 PCI bridge: NVIDIA Corporation Device 0faf (rev a1)
01:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 )

#14

Hi,

“nvidia,enable-power-down” will be part of SOC DTS files.

You can add below line in platform DTS files.
/delete-property/ nvidia,enable-power-down

Thanks,
Manikanta

#15

Hi Manikanta,

I searched the dts files under /hardware/nvidia/soc , thers is no “nvidia,enable-power-down” in any dts file .
And we add the line in platform DTS file as following, but still can’t work.

diff --git a/kernel-dts/porg-platforms/tegra210-porg-pcie.dtsi b/kernel-dts/porg-platforms/tegra210-porg-pcie.dtsi
index fc722f6..f267e18 100644
--- a/kernel-dts/porg-platforms/tegra210-porg-pcie.dtsi
+++ b/kernel-dts/porg-platforms/tegra210-porg-pcie.dtsi
@@ -37,6 +37,7 @@
                                <&{/xusb_padctl@7009f000/pads/pcie/lanes/pcie-4}>;
                        phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3";
 #endif
+                        /delete-property/ nvidia,enable-power-down;
                        nvidia,num-lanes = <4>;
                        status = "okay";
                        nvidia,disable-clock-request;
@@ -47,6 +48,7 @@
                        phys = <&{/xusb_padctl@7009f000/pads/pcie/lanes/pcie-0}>;
                        phy-names = "pcie-0";
 #endif
+                        /delete-property/ nvidia,enable-power-down;
                        nvidia,num-lanes = <1>;
                        nvidia,plat-gpios = <&gpio TEGRA_GPIO(X, 3) GPIO_ACTIVE_HIGH>;
                        status = "okay";
#16

Hi,

My bad, I gave solution for Jetson Xavier. Unfortunately for Nano, there is no DT control to keep PCIe controller enabled. Apply attached kernel patch, compile and flash kernel image it to keep PCIe controller enabled in compliance mode.

Thanks,
Manikanta
0001-PCI-tegra-Disable-controller-power-down.patch (936 Bytes)

#17

Hi ,

The patch cause build break, so I did a little modification as following,

diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
old mode 100644
new mode 100755
index 60958d5ff943..87d6776b33b5
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -2179,7 +2179,7 @@ static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port)
                } while (--timeout);

                if (!timeout) {
-                       dev_info(dev, "link %u down, retrying\n", port->index);
+                       dev_info(dev, "link %u down\n", port->index);
                        goto retry;
                }

@@ -2195,10 +2195,10 @@ static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port)
                } while (--timeout);

 retry:
-               tegra_pcie_port_reset(port);
+               dev_info(dev, "link %u down, retrying\n", port->index);
        } while (--retries);

-       return false;
+       return true;
 }

I still have some questions

  1. Could we apply this patch to formal release to keep PCIe controller always enabled ? Is there have any side effect ?
  2. This patch will impact the Xavier NX or not ?
  3. Could we using this patch to keep TX2-NX PCIe controller enabled in compliance mode?
#18
  1. Could we apply this patch to formal release to keep PCIe controller always enabled ? Is there have any side effect ?

Yes. Power consumption will increase if PCIe controller kept enabled without an endpoint.

  1. This patch will impact the Xavier NX or not ?

No, Xavier devkits has different driver and you can achieve the same with by adding “/delete-property/ nvidia,enable-power-down;”.

  1. Could we using this patch to keep TX2-NX PCIe controller enabled in compliance mode?

Yes.

#20

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