PCIe Status with FPGA card

Hello,

We are trying to access FPGA PCIe card with Key M of Xaiver NX.
The carrier board is customized and I didn’t do something for kernel yet.

We would try to do following link.

Befor that, I want to check is there any problem.
And I’m not sure current status is OK or not.
Please, check the status.

- dmesg | grep pci

[    0.724300] iommu: Adding device 14160000.pcie to group 0
[    0.724987] iommu: Adding device 141a0000.pcie to group 1
[    1.860764] ehci-pci: EHCI PCI platform driver
[    1.860809] ohci-pci: OHCI PCI platform driver
[   12.116244] tegra-pcie-dw 14160000.pcie: Setting init speed to max speed
[   12.117420] OF: PCI: host bridge /pcie@14160000 ranges:
[   12.632123] tegra-pcie-dw 14160000.pcie: link is down
[   12.632503] tegra-pcie-dw 14160000.pcie: PCI host bridge to bus 0004:00
[   12.632511] pci_bus 0004:00: root bus resource [bus 00-ff]
[   12.632518] pci_bus 0004:00: root bus resource [io  0x0000-0xfffff] (bus address [0x36100000-0x361fffff])
[   12.632523] pci_bus 0004:00: root bus resource [mem 0x1740000000-0x17ffffffff] (bus address [0x40000000-0xffffffff])
[   12.632528] pci_bus 0004:00: root bus resource [mem 0x1400000000-0x173fffffff pref]
[   12.632557] pci 0004:00:00.0: [10de:1ad1] type 01 class 0x060400
[   12.632705] pci 0004:00:00.0: PME# supported from D0 D3hot D3cold
[   12.633236] pci 0004:00:00.0: PCI bridge to [bus 01-ff]
[   12.633259] pci 0004:00:00.0: Max Payload Size set to  256/ 256 (was  256), Max Read Rq  512
[   12.633616] pcieport 0004:00:00.0: Signaling PME through PCIe PME interrupt
[   12.633623] pcie_pme 0004:00:00.0:pcie001: service driver pcie_pme loaded
[   12.633739] aer 0004:00:00.0:pcie002: service driver aer loaded
[   12.633908] pcie_pme 0004:00:00.0:pcie001: unloading service driver pcie_pme
[   12.633995] aer 0004:00:00.0:pcie002: unloading service driver aer
[   12.634079] pci_bus 0004:01: busn_res: [bus 01-ff] is released
[   12.634174] pci_bus 0004:00: busn_res: [bus 00-ff] is released
[   12.635507] tegra-pcie-dw 14160000.pcie: PCIe link is not up...!
[   12.636093] tegra-pcie-dw 141a0000.pcie: Setting init speed to max speed
[   12.636373] tegra-pcie-dw 141a0000.pcie: Failed to get 3V slot regulator: -19
[   12.636382] tegra-pcie-dw 141a0000.pcie: Failed to get 12V slot regulator: -19
[   12.744732] OF: PCI: host bridge /pcie@141a0000 ranges:
[   12.852290] tegra-pcie-dw 141a0000.pcie: link is up
[   12.852564] tegra-pcie-dw 141a0000.pcie: PCI host bridge to bus 0005:00
[   12.852572] pci_bus 0005:00: root bus resource [bus 00-ff]
[   12.852579] pci_bus 0005:00: root bus resource [io  0x100000-0x1fffff] (bus address [0x3a100000-0x3a1fffff])
[   12.852584] pci_bus 0005:00: root bus resource [mem 0x1f40000000-0x1fffffffff] (bus address [0x40000000-0xffffffff])
[   12.852589] pci_bus 0005:00: root bus resource [mem 0x1c00000000-0x1f3fffffff pref]
[   12.852615] pci 0005:00:00.0: [10de:1ad0] type 01 class 0x060400
[   12.852746] pci 0005:00:00.0: PME# supported from D0 D3hot D3cold
[   12.853346] pci 0005:01:00.0: [10ee:7014] type 00 class 0x058000
[   12.853529] pci 0005:01:00.0: reg 0x10: [mem 0x00000000-0x000007ff]
[   12.854274] pci 0005:01:00.0: PME# supported from D0 D1 D2 D3hot
[   12.865589] pci 0005:00:00.0: BAR 14: assigned [mem 0x1f40000000-0x1f400fffff]
[   12.865597] pci 0005:01:00.0: BAR 0: assigned [mem 0x1f40000000-0x1f400007ff]
[   12.865623] pci 0005:00:00.0: PCI bridge to [bus 01-ff]
[   12.865631] pci 0005:00:00.0:   bridge window [mem 0x1f40000000-0x1f400fffff]
[   12.865648] pci 0005:00:00.0: Max Payload Size set to  256/ 256 (was  256), Max Read Rq  512
[   12.865702] pci 0005:01:00.0: Max Payload Size set to  256/ 512 (was  128), Max Read Rq  512
[   12.865935] pcieport 0005:00:00.0: Signaling PME through PCIe PME interrupt
[   12.865940] pci 0005:01:00.0: Signaling PME through PCIe PME interrupt
[   12.865946] pcie_pme 0005:00:00.0:pcie001: service driver pcie_pme loaded
[   12.866076] aer 0005:00:00.0:pcie002: service driver aer loaded

- lspci -vv

0005:00:00.0 PCI bridge: NVIDIA Corporation Device 1ad0 (rev a1) (prog-if 00 [Normal decode])
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin A routed to IRQ 35
	Bus: primary=00, secondary=01, subordinate=ff, sec-latency=0
	Memory behind bridge: 40000000-400fffff
	Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
	BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
		PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
	Capabilities: <access denied>
	Kernel driver in use: pcieport

0005:01:00.0 Memory controller: Xilinx Corporation Device 7014
	Subsystem: Xilinx Corporation Device 0007
	Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Interrupt: pin A routed to IRQ 255
	Region 0: Memory at 1f40000000 (32-bit, non-prefetchable) [disabled] [size=2K]
	Capabilities: <access denied>

- lshw

Sorry for the late response, is this still an issue to support? Thanks

Yes, It is.
Could you give me some comment?

Hi,

Current status look fine, link is up and FPGA endpoint is detected.

Thanks,
Manikanta

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