I found this thread about PCIe unaligned access.
How about JetsonNano environment?
Is it possibile to read PCIe at 8, 16 bits by setting byte-enable bit in TLP header?
I found this thread about PCIe unaligned access.
How about JetsonNano environment?
Is it possibile to read PCIe at 8, 16 bits by setting byte-enable bit in TLP header?
Jetson Nano also has this limitation and there is no way out to work with DWord unaligned accesses yet.