We are trying to communicate with an FPGA evaluation board which is installed on the PCIe extension connector on the Jetson TX2 evaluation board.
When the FPGA is configured to PCIe x4 the FPGA is detected by the Jetson on every power on cycle (running lspci on the terminal), while when the FPGA is configured to PCIe x1 it is not detected on each power cycle - the detection seems to be random.
- Is there a way to announce to the Jetson how may lanes the provided PCIe endpoint is to be expected, is a HW configuration (i.e. setting the non-utilized lanes to pull up)?
- Table 16 in NVIDIA Jetson TX2/TX2i OEM Product Design Guide details up to 6 different configurations. How actually a configuration is selected, is there a HW/SW settings which enables us to select it?