PCIe x1, PCIe x4, link fail at PCIe x16

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[Com COM30] (2019-06-12_134603).log (159 KB)

Hi Vidays

Do you have any update for this issue?
Thanks.

Please apply below two patches in the same order and try
Path-1:

diff --git a/drivers/pci/dwc/pcie-tegra.c b/drivers/pci/dwc/pcie-tegra.c
index ee5fbfa2f..1ac64450d 100644
--- a/drivers/pci/dwc/pcie-tegra.c
+++ b/drivers/pci/dwc/pcie-tegra.c
@@ -4540,10 +4540,6 @@ static int tegra_pcie_dw_runtime_resume(struct device *dev)
                val |= APPL_PINMUX_CLKREQ_OUT_OVRD_EN;
                val |= APPL_PINMUX_CLKREQ_OUT_OVRD;
                writel(val, pcie->appl_base + APPL_PINMUX);
-
-               /* Disable ASPM-L1SS adv as there is no CLKREQ routing */
-               disable_aspm_l11(pcie); /* Disable L1.1 */
-               disable_aspm_l12(pcie); /* Disable L1.2 */
        }
 
        /* update iATU_DMA base address */
@@ -4552,6 +4548,12 @@ static int tegra_pcie_dw_runtime_resume(struct device *dev)
 
        reset_control_deassert(pcie->core_rst);
 
+       if (pcie->disable_clock_request) {
+               /* Disable ASPM-L1SS adv as there is no CLKREQ routing */
+               disable_aspm_l11(pcie); /* Disable L1.1 */
+               disable_aspm_l12(pcie); /* Disable L1.2 */
+       }
+
        /* program to use MPS of 256 whereever possible */
        pcie_bus_config = PCIE_BUS_SAFE;
 
@@ -4723,10 +4725,6 @@ static int tegra_pcie_dw_resume_noirq(struct device *dev)
                val |= APPL_PINMUX_CLKREQ_OUT_OVRD_EN;
                val |= APPL_PINMUX_CLKREQ_OUT_OVRD;
                writel(val, pcie->appl_base + APPL_PINMUX);
-
-               /* Disable ASPM-L1SS adv as there is no CLKREQ routing */
-               disable_aspm_l11(pcie); /* Disable L1.1 */
-               disable_aspm_l12(pcie); /* Disable L1.2 */
        }
 
        /* update iATU_DMA base address */
@@ -4735,6 +4733,12 @@ static int tegra_pcie_dw_resume_noirq(struct device *dev)
 
        reset_control_deassert(pcie->core_rst);
 
+       if (pcie->disable_clock_request) {
+               /* Disable ASPM-L1SS adv as there is no CLKREQ routing */
+               disable_aspm_l11(pcie); /* Disable L1.1 */
+               disable_aspm_l12(pcie); /* Disable L1.2 */
+       }
+
        tegra_pcie_dw_host_init(&pcie->pci.pp);
 
        /* restore MSI interrutp vector*/

Patch-2:

diff --git a/drivers/pci/dwc/pcie-tegra.c b/drivers/pci/dwc/pcie-tegra.c
index 1ac64450d..4cd746b8b 100644
--- a/drivers/pci/dwc/pcie-tegra.c
+++ b/drivers/pci/dwc/pcie-tegra.c
@@ -58,8 +58,6 @@
 #define APPL_PINMUX_CLKREQ_OVERRIDE            BIT(3)
 #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN  BIT(4)
 #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE     BIT(5)
-#define APPL_PINMUX_CLKREQ_OUT_OVRD_EN         BIT(9)
-#define APPL_PINMUX_CLKREQ_OUT_OVRD            BIT(10)
 #define APPL_PINMUX_PEX_RST_IN_OVERRIDE_EN     BIT(11)
 
 #define APPL_CTRL                              (0X4)
@@ -4537,8 +4535,8 @@ static int tegra_pcie_dw_runtime_resume(struct device *dev)
 
        if (pcie->disable_clock_request) {
                val = readl(pcie->appl_base + APPL_PINMUX);
-               val |= APPL_PINMUX_CLKREQ_OUT_OVRD_EN;
-               val |= APPL_PINMUX_CLKREQ_OUT_OVRD;
+               val |= APPL_PINMUX_CLKREQ_OVERRIDE_EN;
+               val &= ~APPL_PINMUX_CLKREQ_OVERRIDE;
                writel(val, pcie->appl_base + APPL_PINMUX);
        }
 
@@ -4722,8 +4720,8 @@ static int tegra_pcie_dw_resume_noirq(struct device *dev)
 
        if (pcie->disable_clock_request) {
                val = readl(pcie->appl_base + APPL_PINMUX);
-               val |= APPL_PINMUX_CLKREQ_OUT_OVRD_EN;
-               val |= APPL_PINMUX_CLKREQ_OUT_OVRD;
+               val |= APPL_PINMUX_CLKREQ_OVERRIDE_EN;
+               val &= ~APPL_PINMUX_CLKREQ_OVERRIDE;
                writel(val, pcie->appl_base + APPL_PINMUX);
        }

您好,我最近也在尝试PCIe主从连接设备,能否共享下您所使用的转接板,如果有链接就更好了,不胜感激!