PCIe0 Not Detecting SSD


We are trying to use a mSata SSD on Xavier NX with our custom carrier board.

We have a Marvell 88SE9170 IC on our carrier board and its connected to:


pins of Xavier NX. We attach a mSata disk (Samsung 850 EVO mSATA Series SSD) to mSata connector which connects to marvell IC. We cannot see the disk and the controller on NX.

lspci -vvv
command doesnt show any info.

I cannot see any trace of Marvell IC or disk on dmesg output. You can find dmesg output attached below.

How can we resolve this? Any help will be appreciated.

Thanks in advance.

dmesg.txt (57.0 KB)

Still stuck on this. Will be glad if anyone helps.

I don’t see any issue theoretically and I expect the Marvell controller to get enumerated.
I’m wondering if the issue is to do with missing routing of CLKREQ signal. Could you please add “nvidia,disable-clock-request;” entry under pcie@141a0000 node and check once?

Thanks for the reply.

In file tegra194-soc-pcie.dtsi I have:

 pcie@141a0000 {
                compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
                power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
                reg = <0x00 0x141a0000 0x0 0x00020000   /* appl registers (128K)      */
                       0x00 0x3a000000 0x0 0x00040000   /* configuration space (256K) */
                       0x00 0x3a040000 0x0 0x00040000>; /* iATU_DMA reg space (256K)  */
                reg-names = "appl", "config", "atu_dma";

                status = "okay";

                #address-cells = <3>;
                #size-cells = <2>;
                device_type = "pci";
                num-lanes = <8>;
                linux,pci-domain = <5>;

                clocks = <&bpmp_clks TEGRA194_CLK_PEX1_CORE_5>,
                        <&bpmp_clks TEGRA194_CLK_PEX1_CORE_5M>;
                clock-names = "core_clk", "core_clk_m";

                resets = <&bpmp_resets TEGRA194_RESET_PEX1_CORE_5_APB>,
                         <&bpmp_resets TEGRA194_RESET_PEX1_CORE_5>;
                reset-names = "core_apb_rst", "core_rst";

                interrupts = <0 53 0x04>,       /* controller interrupt */
                                         <0 54 0x04>;   /* MSI interrupt */
                interrupt-names = "intr", "msi";

                pinctrl-names = "pex_rst", "clkreq";
                pinctrl-0 = <&pex_rst_c5_out_state>;
                pinctrl-1 = <&clkreq_c5_bi_dir_state>;

                iommus = <&smmu TEGRA_SID_PCIE5>;
#if LINUX_VERSION >= 414
                iommu-map = <0x0 &smmu TEGRA_SID_PCIE5 0x1000>;
                iommu-map-mask = <0x0>;

                #interrupt-cells = <1>;
                interrupt-map-mask = <0 0 0 0>;
                interrupt-map = <0 0 0 0 &intc 0 53 0x04>;

                nvidia,dvfs-tbl = < 204000000 204000000 204000000  408000000
                                                        204000000 204000000 408000000  666000000
                                                        204000000 408000000 666000000  1066000000
                                                        408000000 666000000 1066000000 2133000000 >;

                nvidia,max-speed = <4>;
                nvidia,disable-aspm-states = <0xf>;
                nvidia,controller-id = <&bpmp 0x5>;
                nvidia,tsa-config = <0x0200b004>;
                nvidia,aux-clk-freq = <0x13>;
                nvidia,preset-init = <0x5>;
                nvidia,aspm-cmrt = <0x3C>;
                nvidia,aspm-pwr-on-t = <0x14>;
                nvidia,aspm-l0s-entrance-latency = <0x3>;

                bus-range = <0x0 0xff>;
                ranges = <0x81000000 0x0 0x3a100000 0x0 0x3a100000 0x0 0x00100000      /* downstream I/O (1MB) */
                          0x82000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xC0000000     /* non-prefetchable memory (3GB) */
                          0xc2000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>;  /* prefetchable memory (13GB) */

                nvidia,cfg-link-cap-l1sub = <0x1c4>;
                nvidia,cap-pl16g-status = <0x174>;
                nvidia,cap-pl16g-cap-off = <0x188>;
                nvidia,event-cntr-ctrl = <0x1d8>;
                nvidia,event-cntr-data = <0x1dc>;
                nvidia,margin-port-cap = <0x194>;
                nvidia,margin-lane-cntrl = <0x198>;
                nvidia,dl-feature-cap = <0x30c>;

I added disable-clock-request but result is the same. I also tried setting num-lanes to 1,2 and max-speed 1,2,3,4.

When NX boots, I see these lines:

[0015.920] I> Plugin-manager override starting
[0015.923] I> node /plugin-manager/fragment-pcie-c5-rp matches
[0015.930] I> node /plugin-manager/fragement-tegra-wdt-en matches
[0015.936] I> node /plugin-manager/fragement-tegra-sdhci-sd-dis matches

Is it possible to these files overriding my PCI settings? If so how can I disable it?

Is it okay to use


on extlinux.conf as FDT with a custom carrier board?

Jetson NX I used is a production version which has a 16GB eMMC.

The plug-in manager just enables the DT node so it is not doing anything malicious.
Did you confirm that your modifications indeed are reflecting in the target by checking the node in /proc/device-tree/pcie@141a0000/?
Also, how is the custom carrier board verified to confirm that there are no issues with it?

Yes, for example after enabling “nvidia,disable-clock-request”, I saw it as “/proc/device-tree/pcie@141a0000/nvidia,disable-clock-request”.

Currently I am waiting for new carrier board. Thank you for your replies.

[quote=“mozturk, post:1, topic:156580”]
Marvell 88SE9170

IS your question resolved?thank you。
I want to use this design,thank you。

IS your question resolved?thank you。
I want to use this design,thank you。