Are there detailed performance counter (events) descriptions ?
L2 cache hit/miss ratio missing ?
I would like to know where I can find the performance counter (events) descriptions.
and does anyone know or have suggestions how I can figure out this information ?
Suppose the application executed 10 global memory instructions.
3 cache hit in L1
5 cache hit in L2 (miss in L1)
2 went to DRAM (miss in L1, L2)
I would like to know a rough ratio of memory accesses…
But I can’t seem to figure out, especially L2, just by looking at the counter results…
Can someone help ?
Thanks !