Hi,
I’m configuring PCIe controller C10 on Jetson AGX Orin 64GB with L4T version 39.2.1 and I’ve hit a problem in the pinmux spreadsheet.
Orin_Pinmux_Config_Template_2.0.xlsm
Issue: For the ball PEX_L10_CLKREQ_N, the Pin Groups columns list the C10 CLKREQ function (pe10) in F0 (F1–F3 reserved), but the Customer Usage dropdown for that row offers only GPIO and unused. The pe10 function cannot be selected, so the generated pinmux dtsi never puts the pad into SFIO mode.
As a result, the macro generates both pads as nvidia,function = "rsvd1" with nvidia,tristate = <TEGRA_PIN_ENABLE>, and additionally places AG6/AG7 in the gpio-input list in the GPIO dtsi — so the PCIe controller neither owns the pads nor can drive them.
Hand-editing the generated files works. After the changes below and a reflash, C10 comes up successfully.
pinmux dtsi:
pex_l10_clkreq_n_pag6 {
nvidia,pins = "pex_l10_clkreq_n_pag6";
- nvidia,function = "rsvd1";
+ nvidia,function = "pe10";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
- nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};
pex_l10_rst_n_pag7 {
nvidia,pins = "pex_l10_rst_n_pag7";
- nvidia,function = "rsvd1";
+ nvidia,function = "pe10";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
- nvidia,tristate = <TEGRA_PIN_ENABLE>;
- nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};
GPIO dtsi — removed both pins from the gpio-input list:
- TEGRA234_MAIN_GPIO(AG, 6)
- TEGRA234_MAIN_GPIO(AG, 7)
Verification:
[ 5.948140] tegra194-pcie 140e0000.pcie: host bridge /bus@0/pcie@140e0000 ranges:
[ 5.948167] tegra194-pcie 140e0000.pcie: MEM 0x3840000000..0x3b27ffffff -> 0x3840000000
[ 5.948174] tegra194-pcie 140e0000.pcie: MEM 0x3b28000000..0x3b2fffffff -> 0x0040000000
[ 5.948181] tegra194-pcie 140e0000.pcie: IO 0x002e100000..0x002e1fffff -> 0x002e100000
[ 5.949052] tegra194-pcie 140e0000.pcie: iATU: unroll T, 8 ob, 2 ib, align 64K, limit 32G
[ 6.153450] tegra194-pcie 140e0000.pcie: PCIe Gen.1 x1 link up
[ 6.257458] tegra194-pcie 140e0000.pcie: PCIe Gen.1 x1 link up
[ 6.270058] tegra194-pcie 140e0000.pcie: PCI host bridge to bus 000a:00
Questions:
- Why are the pe10 functions excluded from Customer Usage for these balls when they are valid and work once set?
- Is this a known issue with this spreadsheet revision, or is there a revision where C10’s sidebands are selectable for this module?
- Since hand edits are lost whenever the macro regenerates the dtsi files, what is the recommended way to carry this configuration forward?
Happy to attach the full generated dtsi files or the schematic for the C10 sideband nets.
Thanks.
