PEX_WAKE_N/D48 as a GPIO Output

I need to use PEX_WAKE_N/D48 as a GPIO Output on my custom design.

Looking at Figure 23 (PCIe Connection Example) from the NVIDIA Jetson TX2 Series OEM Product Design Guide (version 20190606) it looks like PEX_WAKE#/D48 has an internal pull-up resistor to VDD_3V3_SYS (this also corresponds with the description of the pin in the Module Connector Pin Description Table 92). The block in Figure 23 says “Jetson” at the top, but I am assuming that it is applicable to the Jetson TX2 module, also. Is that correct?

If that diagram is correct for the Jetson TX2, what is the value of the pull-up resistor on PEX_WAKE_N?

Additionally, I have found that by default PADCTL_PEX_CTL_PEX_WAKE_N_0 (0x02437008) has E_IO_HV[5] set to ENABLE(1) for 3.3V High Voltage Operation. However, when I use GPIO A.02 (#322) as an output and set it HIGH(1) the external device connected to the signal does not register the value of the signal as HIGH(1). When I set PADCTL_PEX_CTL_PEX_WAKE_N_0 E_IO_HV[5] to DISABLE(0), the external device connected to the signal does register as HIGH(1) when the GPIO is set HIGH(1). If I’m using PEX_WAKE_N/D48 as a GPIO Output signal, is there any danger to the module or the processor from disabling E_IO_HV in the pad control register for PEX_WAKE_N?

Is there a better method or some other secret register setting (i.e., E_OD[11], E_SCHMT[12], PM[1:0], etc.) I need to use if my design needs to use PEX_WAKE_N/D48 as a GPIO Output and work properly?

There is a 56kohm pull up in module on pin D48.

But the pinmux does not allow this pin to be a GPIO…

It does support pinmux. I have referenced the padctl register, used the padctl to configure it as a GPIO, and seen the pin operate properly as both an output and an input GPIO signal with A.02 (#322).

Could you please answer the other questions I have listed?

Is there anyone on the NVIDIA design team that could look at the questions I have in this post about E_IO_HV?

Pin D48 can’t be used as GPIO. The pinmux sheet should be followed well as it is validated and safe for customer to do some change as listed. Please follow guide to do pin configuration and don’t change register value as will.

There are seven pins in the PEX_CTL that can be used as GPIOs:

For a custom carrier board that does not have PCIe support, if these pins are used as output GPIOs, what is the effect on the Jetson TX2 module of disabling the 3.3V Tolerance (E_IO_HV) for each of these pins?

Hi, please refer to the pinmux sheet in DLC, these pins can’t be set as GPIO type.

If 3.3v tolerance is disabled, the pins can only be 1.8v input.

The pinmux sheet is incomplete and has inaccurate information. Please refer to the TRM to find the corresponding pins and the full ability of the SoC. The spreadsheet has many mistakes and issues for anyone doing a custom board.

I’m not using the pins as input. I am using them as 1.8V output. Everything seems to be working fine without issue. Some power is being wasted but it does not amount to much since the pull-up on the SoM is a weak 56kohm.

The TRM is chip level doc, not all function/characters of it are available on Jetson platform. Pinmux sheet is for Jetson, so it may be not full ability as said in TRM. Can you share the mistakes found in pinmux sheet? Thanks a lot.