I need to use PEX_WAKE_N/D48 as a GPIO Output on my custom design.
Looking at Figure 23 (PCIe Connection Example) from the NVIDIA Jetson TX2 Series OEM Product Design Guide (version 20190606) it looks like PEX_WAKE#/D48 has an internal pull-up resistor to VDD_3V3_SYS (this also corresponds with the description of the pin in the Module Connector Pin Description Table 92). The block in Figure 23 says “Jetson” at the top, but I am assuming that it is applicable to the Jetson TX2 module, also. Is that correct?
If that diagram is correct for the Jetson TX2, what is the value of the pull-up resistor on PEX_WAKE_N?
Additionally, I have found that by default PADCTL_PEX_CTL_PEX_WAKE_N_0 (0x02437008) has E_IO_HV set to ENABLE(1) for 3.3V High Voltage Operation. However, when I use GPIO A.02 (#322) as an output and set it HIGH(1) the external device connected to the signal does not register the value of the signal as HIGH(1). When I set PADCTL_PEX_CTL_PEX_WAKE_N_0 E_IO_HV to DISABLE(0), the external device connected to the signal does register as HIGH(1) when the GPIO is set HIGH(1). If I’m using PEX_WAKE_N/D48 as a GPIO Output signal, is there any danger to the module or the processor from disabling E_IO_HV in the pad control register for PEX_WAKE_N?
Is there a better method or some other secret register setting (i.e., E_OD, E_SCHMT, PM[1:0], etc.) I need to use if my design needs to use PEX_WAKE_N/D48 as a GPIO Output and work properly?