PEX1 Lane 0 and USB_SS0

Autonomous Machines Jetson & Embedded Systems Jetson TX2
1

I made a carrier board that is pretty close to the TX2 Dev Kit board.

I have everything working except the PCIe-mini card that I used instead of the M.2 Key E connector on the Dev Kit.

I finally figured out how to change the ODM Data to 0x90000, and now the PCIe-mini (M.2) card works but my USB hub that is attached to USB_SS0 and USB1 has no upstream link. I had no idea that the M.2 connector and the USB3.0 jack on the Dev Kit would be mutually exclusive. Bad assumption.

I noticed in the adaptation guide, that there is no configuration listed that has PEX1 Lane 0 and USB_SS0 at the same time. Is there one possible? What happened to USB1? We could live for now with just USB2.0 as the upstream port for my hub.

Help!!!

Thanks!!
Bob

2

Hi BConklin,

Yes, these two are mutually exclusive to each other. USB_SS0 and PCIe are sharing the same UPHY in tegra soc. If you enable PCIe on M.2 (devkit), you could only use usb2.0 on that port.

3

So how do I re-enable USB1?

4

Hi,

Just reverse what you’ve done (ODMdata).

5

Changing odm data killed USB SS0 and the USB1 ports. I want to get the hs port back. I suspect a fragment related to the PCIe, but I dont see anything at all for that port. What is it called?

6

I got lucky. I re-enabled usb3-std-A-port2 in the TX2i plugin-manager.dtsi, and the USB1 port came back. PCIe for the M.2 is still there.

Linux_for_Tegra/sources/hardware/nvidia/platform/t18x/common/kernel-dts/t18x-common-plugin-manager/tegra186-quill-p3489-1000-a00-plugin-manager.dtsi

Changed “usb3-std-A-port2” from “status = “disabled”;” to “status = “okay”;”

    plugin-manager {
            fragment-500-e3325-pcie {
                    enable-override-on-all-matches;
                    ids = ">=3489-0000-200";
                    odm-data = "enable-pcie-on-uphy-lane0";
                    override@0 {
                            target = <&{/xhci@3530000}>;
                            _overlay_ {
                                    phys = <&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(0)>,
                                            <&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(1)>;
                                    phy-names = "utmi-0", "utmi-1";
                            };
                    };
                    override@1 {
                            target = <&tegra_xusb_padctl_pinmux_default>;
                            _overlay_ {
                                    usb3-std-A-port2 {
                                            status = "okay";
                                    };
                            };
                    };

                    override@2 {
                            target = <&tegra_main_gpio>;
                            _overlay_ {
                                    pcie0_lane2_mux {
                                            status = "okay";
                                    };
                            };
                    };
            };
7

Sorry that I didn’t notice your term “USB1” mean the usb2.0 port.