Pipeline architecture and Instruction Set of Pascal architecture

Accelerated Computing CUDA CUDA Programming and Performance
1

I am doing a project in an Advanced Computer architecture course, where we have to review the pipeline architecture of the processor in detail, along with its instruction set architecture(ISA). In the white paper for the Pascal architecture, they have shown the structure upto SMs, but where can we see the architecture of the SM itself, the fp and int cores which are used by it? Is it possible to break it down to the level where we can see the individual pipeline stages, what is happening in them etc. along the lines of http://submit4m.nl/bestanden/jeroen/patterson_book.pdf

Also I think PTX is the ISA used by CUDA to parallelize operations, can we get the native instruction set architecture of the processors?

2

https://docs.nvidia.com/cuda/cuda-binary-utilities/index.html
4. Instruction Set Reference

That’s as much information as NVIDIA is willing to provide. since the native Pascal ISA is quite similar to the native Maxwell ISA, you might get some additional insights by looking at the source for Scott Gray’s maxas SASS assembler: https://github.com/NervanaSystems/maxas

3

Thank you, any idea about the pipeline modules?

4

Except for some morsels sprinkled across the official documentation, NVIDIA does not publicly document the microarchitecture of its GPUs. There have been a few papers published by people who have tried to reverse engineer various aspects of GPU architecture (Google Scholar is your friend), but to my knowledge none of these has described the internal architecture of SMs down to the pipeline level.