Depending on the pix_clk_hz setting, the image of the AGX Orin CSI-2 input may or may not be captured.
I would like to know how to calculate the correct pix_clk_hz setting in the device tree.
See below for details.
In the application we are developing, the FPGA’s CSI-2 output is connected to the AGX Orin’s CSI-2 input. D-PHY x 2 lanes are used and the maximum data rate target is 2400Mbps/lane. The data format is RAW 8-bit.
First of all, as an experiment, I tried transferring some images from the FPGA to Orin at 1280Mbps/lane, and there was no problem to capture the images. The pix_clk_hz setting value at this time was 320,000,000. The formula is 1,280,000,000 bps / 8 bit * 2 lane = 320,000,000.
Then I changed the transfer data rate to the target, 2400Mbps/lane, and could not capture the images. The pix_clk_hz setting value at this time was 600,000,000. The formula is the same as above.
Therefore, as an experiment, I changed only the pix_clk_hz setting value to 320,000,000 without changing the transfer data rate, and I was able to capture the images without any problems.
If the formula is correct, the pix_clk_hz setting value should be 600M, but it doesn’t work at 600M and works at 320M. I don’t understand this.
How do I calculate the correct pix_clk_hz setting?
Thank you in advance for your cooperation.