Pix_clk_hz setting value for AGX Orin CSI-2 camera input

Depending on the pix_clk_hz setting, the image of the AGX Orin CSI-2 input may or may not be captured.
I would like to know how to calculate the correct pix_clk_hz setting in the device tree.

See below for details.

In the application we are developing, the FPGA’s CSI-2 output is connected to the AGX Orin’s CSI-2 input. D-PHY x 2 lanes are used and the maximum data rate target is 2400Mbps/lane. The data format is RAW 8-bit.

First of all, as an experiment, I tried transferring some images from the FPGA to Orin at 1280Mbps/lane, and there was no problem to capture the images. The pix_clk_hz setting value at this time was 320,000,000. The formula is 1,280,000,000 bps / 8 bit * 2 lane = 320,000,000.

Then I changed the transfer data rate to the target, 2400Mbps/lane, and could not capture the images. The pix_clk_hz setting value at this time was 600,000,000. The formula is the same as above.

Therefore, as an experiment, I changed only the pix_clk_hz setting value to 320,000,000 without changing the transfer data rate, and I was able to capture the images without any problems.

If the formula is correct, the pix_clk_hz setting value should be 600M, but it doesn’t work at 600M and works at 320M. I don’t understand this.
How do I calculate the correct pix_clk_hz setting?

Thank you in advance for your cooperation.

hello h.taniyama,

please refer to camera programming guide, you may see-also SerDes Pixel Clock session.
for Orin series, deskew calibration is a must if data-rate > 1.5 Gbps, Else the camera firmware will continue to wait for deskew signal from the sensor side. it’ll enable pixel parser when deskew calibration has completed.

hence,
please check you’ve sending deskew signaling.

Thank you for your prompt reply.

Yes, the FPGA has already sent the deskew signal for the skew calibration. So, the images have been captured at 2400Mbps/lane with pix_clk_hz=320,000,000.

However, it doesn’t work at 2400Mbps/lane with pix_clk_hz=600,000,000. Only the pix_clk_hz setting value is different.

I just want to know how to calculate the correct pix_clk_hz setting.

Thanks.

hello h.taniyama,

you may refer to Sensor Pixel Clock for different formulas to calculate the pixel clock.

BTW,
there’s some known issue that Argus waits for signal too early. could you please workaround by configure sensor state as standby (not streaming), then switch the sensor state to stream after a short while.

Hi Jerry-san,

I already refer to Sensor Pixel Clock and I am using the formula written on the page.

The page mentions :

Using sensor CSI lane output rate:
pixel_clk_hz = sensor data rate per lane (Mbps) * number of lanes / bits per pixel

In our application :
FPGA data rate = 2400 Mbps (per lane)
Number of lanes = 2
Bit per pixel = 8
Then pixel_clk_hz = 2400 Mbps x 2 / 8 = 600,000,000

So, I think that the correct value is 600,000,000 and I set the value to pix_clk_hz in the device tree. But, unfortunately, it doesn’t work.
However, as mentioned in the first post, the combination of “FPGA data rate = 2400Mbps” and “pix_clk_hz = 320,000,000” works fine. Calculating from the sensor output size and the frame rate at this time, the data rate is definitely 2400Mbps/lane.

I would like to know why it doesn’t work with the correct setting, 600M, but works with an incorrect setting, 320M.

Thanks.

hello h.taniyama,

I assume you update device tree to apply pixel_clk_hz changes, right?
may I know your steps to update device tree.

could you please also check sysnode to confirm you had change applied correctly.
for example,
# cat /proc/device-tree/i2c@3180000/tca9546@70/i2c@0/imx185_a@1a/mode0/pix_clk_hz

Hi Jerry-san,

Yes, I update device tree to change pix_clk_hz. I think the update procedure is fine because the changes are applied correctly as shown below.

When pix_clk_hz is set to 320M :

$ cat /proc/device-tree/i2c@3180000/18MP90FPS0_e@10/mode0/pix_clk_hz
320000000

When pix_clk_hz is set to 600M :

$ cat /proc/device-tree/i2c@3180000/18MP90FPS0_e@10/mode0/pix_clk_hz
600000000

Thanks.

BTW, as an experiment,
I checked the maximum limit of pix_clk_hz. Details are provided below. It seems that the CSI-2 data rate is limited at around 1.5Gbps/lane. The actual CSI-2 data rate is 2.4Gbps/lane output by the FPGA.

Therefore, while the AGX Orin’s hardware supports up to 2.5Gbps/lane, the software seems to have a restriction of the CSI-2 data rate up to 1.5Gbps/lane. The software is the latest version, Jetson Linux 35.1.


When the images can be captured :
pix_clk_hz = 375000499
Calculated CSI-2 data rate = 375000499 x 8bit / 2lane = 1,500,001,996 bps/lane

When the images can not be captured :
pix_clk_hz = 375000500
Calculated CSI-2 data rate = 375000500 x 8bit / 2lane = 1,500,002,000 bps/lane


Could you please check this issue with your software guys?

Thanks.

hello h.taniyama,

did you send deskew signal when you increase data rate?
for Orin series, deskew calibration is a must if data-rate > 1.5 Gbps, Else the camera firmware will continue to wait for deskew signal from the sensor side. it’ll enable pixel parser when deskew calibration has completed.

Hi Jerry-san,

Thanks to you, this issue has been resolved.

The FPGA was outputting the deskew signal, but the output timing was wrong. The deskew signal was being output just after the FPGA booted. I thought it was too early, so I changed the output timing of the deskew signal from the FPGA to just before the first image capture, and now it works without any problems.

Thank you so much.

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