PMIC I2C access from user space

Background:

We have a Jetson-esque system and use the watchdog aboard to PMIC.
The PMIC is accessed via an I2C device (it uses the MFD i2c interface) in a daemon that services the watchdog every 2 seconds. The watchdog timeout is set to 45 seconds.

The PMIC pre-watchdog IRQ is hooked up to a GPIO on the Tegra to give 8 seconds notice before the PMIC Watchdog expires. During this 8 second period system state is stored such that the data could be used to determine why the watchdog fired.

Problem:
The watchdog servicing seems to work most of the time - by most I means for days on hundreds of devices. About 1 device per day fires and the data retrieved indicates that the watchdog could not be serviced. The I2C transactions fail with a timeout.

After much digging the DVFS code appears to use I2C without any awareness of the MFD I2C driver. Also it seems to access it in a manner that is not apparent from the TRM that I have. By that I mean the MMIO looking interface here (I may have simply missed that piece in the docs though):

arch/arm/mach-tegra/tegra_cl_dvfs.c
static inline u32 cl_dvfs_i2c_readl(struct tegra_cl_dvfs *cld, u32 offs)
288 {
289 return __raw_readl(cld->cl_i2c_base + offs);
290 }
291 static inline void cl_dvfs_i2c_writel(struct tegra_cl_dvfs *cld,
292 u32 val, u32 offs)
293 {
294 __raw_writel(val, cld->cl_i2c_base + offs);
295 }

So questions:

  • Is anybody using the PMIC watchdog, or accessing it via I2C?
  • If so have you every seen random I2C hangs?

My suspicion is the I2C state machine suffers some kind of problem due to being accessed from 2 places in the kernel concurrently.

Is there further documentation/information available on the method DVFS uses to access I2C?

Cheers,
G.

Hello, Thnker:
What version of L4T package you are using?
Some issues related to PMIC access during reboot have already been fixed in R21.4.

If you are using the R21.4, would you please provide the ‘I2C hang’ log during test?

br
ChenJian