Porting ALC5616 audio codec to Jetson Thor

Robotics & Edge Computing Jetson & Embedded Systems Jetson Thor
1

Hi NV Team

We are currently porting the ALC5616 audio codec to our custom carrier board with the Thor SOM, and we have encountered some issues during the process.

The RT5616 driver is successfully probed and correctly registered under the APE node. When playing audio (e.g., YouTube), the I2S4 data waveform changes according to the volume level, which indicates that I2S data output is functioning properly.
However, when measuring the analog outputs (AUDIO_HPO_R/L and LOUTL_P/N), there is no analog audio signal at all.

We would like to confirm whether there are still missing modifications in the device tree or source code (attached file: rt5616.tar.gz).
In addition, the MCLK signal we measured does not look correct. We referenced the RT5640 implementation on the NVIDIA reference board and configured the codec to use an external MCLK, but the measured MCLK waveform looks more like noise and its frequency seems incorrect.

Fig 1 Schematic

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Fig 2 Sound Systeme

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The yellow signal is BCLK (3.07 MHz). The orange signal is MCLK.

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The attached file is the source code for rt5616.

rt5616.tar.gz (110 KB)

4

Moving to Jetson Thor forum.

6

Hi,

Could you provide the clock summary dump to understand the clock rate configs from target during active usecase

Audio Setup and Development — NVIDIA Jetson Linux Developer Guide

cat /sys/kernel/debug/clk/clk_summary > ~/clock.txt

10

clock.txt (142.7 KB)
Hi
I have attached the file.

11

Sorry, I don’t see any I2S in enable state in dump, does this taken while playback is active?. If not could you re attach

12

Hi

Sorry, I have reattached the file. I played some music on YouTube.

clock2.txt (142.7 KB)

13

From the dump, I could see I2S4 at 3.07MHz and AUD_MCLK at 49.152MHz, these both rates are correct for a multiple of 8KHz rate playback. I believe your playback is with 48KHz, 2ch, 32bit format.

So, BCLK is matching with the scope data. I believe the MCLK is showing 26.99MHz on ur scope image which seems not matching with the clock summary dump.

The dump shows Aud_MCLK is not in enabled state. We need to check the Codec DT node on whether we pass the aud_mclk entry to make use of it

    pll_a1                           1       1        0        983039611   0          0     50000      Y      sound                           pll_a                    
                                                                                                              deviceless                      no_connection_id         
       plla1_out1                    1       1        0        49151980    0          0     50000      Y         sound                           plla_out0                
                                                                                                                 deviceless                      no_connection_id         
          aud_mclk                   0       0        0        49151980    0          0     50000      Y            deviceless                      no_connection_id         
          dspk1                      0       0        0        49151980    0          0     50000      Y            deviceless                      no_connection_id         
          dmic1                      0       0        0        49151980    0          0     50000      Y            deviceless                      no_connection_id         
          i2s8                       0       0        0        49151980    0          0     50000      Y            deviceless                      no_connection_id         
             i2s8_pad_m              0       0        0        49151980    0          0     50000      Y               deviceless                      no_connection_id         
          i2s7                       0       0        0        49151980    0          0     50000      Y            deviceless                      no_connection_id         
             i2s7_pad_m              0       0        0        49151980    0          0     50000      Y               deviceless                      no_connection_id         
          i2s6                       0       0        0        49151980    0          0     50000      Y            deviceless                      no_connection_id         
             i2s6_pad_m              0       0        0        49151980    0          0     50000      Y               deviceless                      no_connection_id         
          i2s5                       0       0        0        49151980    0          0     50000      Y            deviceless                      no_connection_id         
             i2s5_pad_m              0       0        0        49151980    0          0     50000      Y               deviceless                      no_connection_id         
          i2s4                       1       1        0        3071998     0          0     50000      Y            i2s@92b0000                     no_connection_id         
                                                                                                                    i2s@92b0000                     no_connection_id
14

tegra264-p4071-0000+p3834-0008-nv-d331.txt (325.0 KB)

clock3.txt (143.1 KB)

Hi
The attached file are all device tree and new clk_summary.

I forgot to include the clocks and clock-names properties in the previous file, but even after adding them, the MCLK value is still incorrect.

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15

The clock dump is without youtube playback, Could you provide the dump during the playback.

16

clock4.txt (143.1 KB)

Hi

I have reattached the file.

17

Hi
I think the correct MCLK frequency should be 12 MHz,but the orange signal’s frequency MCLK is much lower than the signal’s yellow’s frequency BCLK(3MHZ) frequency. It seems that the MCLK is not being activated at all.

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18

That’s right, MCLK is not being enabled is the issue, this clock is handled by codec driver. Could you enable the print and check if clock enable is indeed called in codec driver side.

Your info shows machine driver is requesting 12.28MHz which is correct for 48KHz with 256Fs scaling for MCLK.

19

Hi

After adding the following function in my driver , the MCLK can now be successfully enabled (12MHZ). However, the MCLK remains enabled all the time, even when no audio is being played, and the analog audio output is still not present.

function:
clk_set_rate(rt5616->mclk, freq);
clk_prepare_enable(rt5616->mclk);

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20

You can try moving this into pm runtime resume/suspend callback, so MCLK would be enabled only during the usecase enabled. Need to enable clock in resume and disable in suspend to maintain refcount.

Are you saying even after enabling MCLK clock, the audio output was not there?

21

Hi

Yes, my analog output still isn’t coming out. I am checking whether there are any errors in the RT5616 register settings.

22

What is the status of I2S DOUT signal from Tegra to codec. Are you able to see valid signal but only from codec we are not able to hear output?