The TX1 has 12 mipi lanes, so if we could just give each camera it’s own lane, that would work really well.
I noticed that this Cypress application note AN75779
Has a section on connecting 2 image sensors to a single MIPI receiver.
The CX3 device has a 2-lane MIPI receiver, it connects the cameras to the same clock, and then has each camera send data on one of the MIPI lanes. Basically, the two 1-lane cameras in a stereo pair pretend to be a single 2-lane camera. The resulting stream has the data from from the two cameras interleaved per pixel, but this could be split on the GPU pretty easily/efficiently.
Do you think that a similar setup could work on the Tegra? It has 12 MIPI lanes, and so could potentially directly support 6 pairs of cameras.
From what I understand, the other SOC’s support a “3D camera mode” which provides this capability.