Power-down sequence regarding ORIN SOC module


We’re designing our own board based on the Jetson ORIN SOC module. Just want to know if our custom design is not complying with the power down sequence @ controlled case, are there any risks by just removing the VDD_VIN power supply, and if we doing so, the SOC will enter the uncontrolled power down sequence right?

Besides, from the ORIN DG datasheet. there’s a note under uncontrolled power sequence diagram, it says

SYS_VIN_MV must go below 100 mV before system can be powered on again.

If we power on again when this requirement is not satisfied, what will happen to the SOC moudle?


Please fulfill the sequence requirement as listed in DG, that’s important to system power on/off and to protect hardware. We don’t have suggestion to the design that violates that.

so what does the uncontrolled power off sequence diagram really mean?

That sequence means custom design should provide enough capacitance to let system complete power off sequence when meet power loss suddenly. That’s only for occasional power loss situation, not for a constant custom design.

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