Power on conditions

Hi Jetson experts,
On Section 5.1 power sequencing of Orin design guide, it states that VDDIN_PWR_BAD_N shall stay low until both SYS_IN_HV/MV (not gated )are valid. Please note that VDDIN_PWR_BAD_N = VIN_PWR_BAD_N according to carrier board schematics. Design guide power sequencing states that from Sys_Vin_HV stable state to Module Power on requirement is 50ms.

I have a few questions would like your help.

1.During power up, after U69 in the carrier board schematic de-assert Vin_Pwr_bad_n in open drain status ( I mean it is floating), will Vin_Pwr_bad_n be pulled up by 5V_AO through Q526 (please see page 6 of schematic) leakage current?

2.On carrier board/dev kit, during power up, after U69 de-assert Vin_Pwr_bad_n , does the Button MCU U79 count the timing between VIN_PWR_ON and MODULE_POWER_ON? Design guide power sequencing states that from Sys_Vin_HV stable state to Module Power on requirement is 50ms. Does it need to wait Vin_Pwr_bad_n to be pulled high after it is de-asserted from U69 (Please see page 32 of schematics? If pulling Vin_Pwr_bad_n High is need, how soon it can be pulled referencing to Sys_Vin_HV?

Another question, UART7 pins are connected to the high density connector’s pinB48 and B49 on the carrier board schematics, page 5. Design guide marked these two pin as RSVD. Should I follow design guide or schematic?

Yet another similar questions to the UART question, pin L44 and L45 on page 5 of schematics are I2C but design guide marked them as RSVD. Should I follow design guide or schematic?

Thanks,
Paxon

I will pass this issue to our HW design team to do the suggestion, please stay tuned.

Thank you passing the questions to your HW team.
Further to the above questions, AGX Orin design guide DG-10653-001_v1.1, does not have a section for “Power-On No MCU designs” like AGX Xavier did. An earlier Forum post in March 2022 indicated thT Orin had no plan for this Power On scheme yet: Jetson AGX Orin Power-On No MCU Design
Has there been any No-MCU power on plan for Orin today?

If that plan has not yet been available, do you recommend monitoring both Sys_Vin_HV and Sys_Vin_HM along with Vin_PWR_Bad_N to implement no-MCU power on scheme? Welcome other recommendations.

Thanks,

Looking for Reference design of “No-MCU & Auto-power on” for AGX Orin Module.

See also: VCC_SRC and VCC_SRC_FET on Orin Carrier board - Jetson & Embedded Systems / Jetson AGX Orin - NVIDIA Developer Forums

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