Power On Sequence

Dear Nvidia Team

Figure 5-2 in the Jetson AGX Orin Design Guide shows a delay between CARRIER_POWER_ON and SYS_RESET_N, which is at least 12 ms. In the same figure, there is also a delay between MODULE_POWER_ON and CARRIER_POWER_ON which is smaller than 5ms. How does this correlate to Figure 5-9 and Table 5-4? There, the delay between MODULE_POWER_ON and CARRIER_POWER_ON is 100 ms (typical). Also SYS_RESET_N is given as 0 or 1, and not asserted before CARRIER_POWER_ON is high as in Figure 5-2.
Can you please explain these differences? Is SYS_RESET_N always de-asserted after CARRIER_POWER_ON?
Thank you for the clarification.

Best regards

Dear NVidia Team

Any update on this topic?
Thank you.

Figure 5-2. Power On Sequence (Power Button Case)
This is power on use power button, system off to on.
Figure 5-9. Power-On to OFF Power Button Held Low > 10 Seconds
This is use power button press >10s to force shutdown, system on to off.

Off to on, on to off, they are totally different cases.

Hi JimWang

Thank you for your answer.
In the Jetson AGX Orin Series Design Guide v1.4, Figure 5-9 is “Power-OFF to On Sequence Auto Power-On Case” and so is Table 5-4. Please check again.

The latest version is 1.6
Figure 5-9. Power-OFF to On Sequence Auto Power-On Case
This system auto power on when main power connected, do need press power button.

We would like to know the relation between CARRIER_POWER_ON and SYS_RESET_N. As mentioned in the first post, the SYS_RESET_N should be deasserted 12 ms after CARRIER_POWER_ON. Is this always true? Because in figure 5-9 (Design Guide v1.6), the difference between CARRIER_POWER_ON and MODULE_POWER_ON is 100 ms and not smaller than 5ms.

SYS_RESET_N need delay refer to MODULE_POWER_ON, don’t need refer CARRIER_POWER_ON.
CARRIER_POWER_ON generate by module.
MODULE_POWER_ON to CARRIER_POWER_ON <= 5ms, not conflict with max 100ms.

Does this mean that SYS_RESET_N can be de-asserted before CARRIER_POWER_ON becomes active? We measured the signals on a custom carrier and we saw that SYS_RESET_N is de-asserted around 12ms after CARRIER_POWER_ON. As both Signals CARRIER_POWER_ON and SYS_RESET_N are generated by the module, we need to know the timing between them.

SYS_RESET_N de-assert by sequencer on module.
CARRIER_POWER_ON generate after module power good.
Both controlled by module, carrier can do nothing and don’t need care about timing between them.

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