1.Current situation: There is no MCU in our self-designed carrier board. During the test, we found that the timing of POWER_EN and SYS_RESET* did not meet the requirement of greater than 80ms. The design guidelines require greater than 80ms。
2.Question: Is this timing mandatory? Do we have to meet this timing?
3.I understand that POWER_EN controls the power-on of Nano module PMIC. After PMIC is powered on, SYS_RESET will be pulled up by the module to control the power supply of the carrier board (VDD_3V3_SYS,VDD_1V8). The timing between POWER_EN and SYS_RESET is determined by the module itself and we can’t contorl it.
Here is the Measured timing
Yes, it is controlled by module not by carrier. It is a typical value not mandatory as you can see in Figure 6-9. Power-Off to On Sequence Auto Power-On Case.
So here are 3 more questions to help answer:
1.There’s no problem with our test timing between POWER_EN and SYS_RESET*,right?
2.What are the VIH and VIL thresholds of POWER_EN?I can’t find this parameter in the datasheet and design guide.
3.I want know why this actual timing different from design guide’s typical timing?
Thanks.