The Tegra X2 IC ball name is QSPI_SCK. The frequency of 1.3 MHz is right in line with what frequency some QSPI chips might communicate at. My guess is that that the Tegra X2 Boot ROM, or other early MB code, is doing a QSPI read/check operation and the pin has not been configured properly. Are you sure you have a properly programmed BCT on your device to put G8/PR.00 in GPIO mode configuration with a GPIO output setting?
If you do have it configured properly, then it might be something out of your control. Someone else should be able to check their board and see the same thing you are if it is completely out of your control and the Boot ROM is doing it before it has ever configured the pinmuxing.