Hi all,
I am testing PWM directly in Jetson Xavier board, I have few concerns during testing for which I need your support.
Test with below configuration:
- pwmchip0 --> c340000.pwm --> PWM4 --> FAN CONTROL
- pwmchip1 --> 32c0000.pwm --> PWM5 --> Pin18 of 40pins Header
- pwmchip2 --> 32f0000.pwm --> PWM8 --> Pin13 of 40pins Header, LCD_BLT_PWM
- pwmchip4 --> 39c0000.pwm --> TACH --> Tachometer function
I was able to export PWM5 and PWM8 to /sys/class/pwm/pwmchipX, X is as above, then set-up their period/duty_cycle are the same: period=2600000, duty=2400000. Then enable PWM5/PWM8 for pulses out, I observed by oscilloscope the pulses out for both PWM5/PWM8.
Point #1: at the beginning phase deviation between PWM5, PWM8 was 1ms, but it was shifting slowly over the time, the phase deviation was not always fixed. From my understanding, they are hardware PWM modules using fixed clock_source, there should not be phase shift. Is this correct?
Point #2: digging deeply for PWM clock_source from clk_tree, I figured out that PWM clocked source for PWM5–> CLK_M:19.2Mhz but PWM8–>PLLP:408Mhz. Please let me know how to change their clock source in device tree for PWM modules, so that it can be loaded during startup.
<b>tegra194-soc-pwm.dtsi</b>
tegra_pwm5: pwm@32c0000 {
compatible = "nvidia,tegra194-pwm";
reg = <0x0 0x32c0000 0x0 0x10000>;
nvidia,hw-instance-id = <0x4>;
clocks = <&bpmp_clks TEGRA194_CLK_PWM5>;
clock-names = "pwm";
#pwm-cells = <2>;
resets = <&bpmp_resets TEGRA194_RESET_PWM5>;
reset-names = "pwm";
status = "disabled";
};
...
tegra_pwm8: pwm@32f0000 {
compatible = "nvidia,tegra194-pwm";
reg = <0x0 0x32f0000 0x0 0x10000>;
nvidia,hw-instance-id = <0x7>;
clocks = <&bpmp_clks TEGRA194_CLK_PWM8>;
clock-names = "pwm";
#pwm-cells = <2>;
resets = <&bpmp_resets TEGRA194_RESET_PWM8>;
reset-names = "pwm";
status = "disabled";
};
<b>tegra194-clock.h</b>
#define TEGRA194_CLK_PWM1 105U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */
#define TEGRA194_CLK_PWM2 106U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */
#define TEGRA194_CLK_PWM3 107U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */
#define TEGRA194_CLK_PWM4 108U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */
#define TEGRA194_CLK_PWM5 109U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */
#define TEGRA194_CLK_PWM6 110U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */
#define TEGRA194_CLK_PWM7 111U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */
#define TEGRA194_CLK_PWM8 112U
static const char *mux_pllp_pllc_clk32_clkm[] = {
"pll_p", "pll_c", "clk_32k", "clk_m"
};
...
MUX("pwm", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_PWM, 17, TEGRA_PERIPH_ON_APB, tegra_clk_pwm),
Point #3
PWM1–> 3280000 → Pin15 of 40pins header
It has not been added to any pwmchip controller. Please let me know the steps to use PWM1.
Point #4
Is it possible/any solution to count number of pulses generated from PWM module.
Thanks for your support!