I want to communicate with a NOR QSPI device.
I see that although H7, E8, G8, H8 pins can be used for this interface, they support only 2 out of 4 IOs the QSPI protocol needs.
There are 3 more pins QSPI_IO2, QSPI_IO3, QSPI_COMP which appear to have no pins.
What should I do?

I encountered the same issue on the Jetson TX2 SoM. I solved the problem by changing several lines in the qspi_mtd.c driver from QUAD to DUAL.

diff --git a/drivers/mtd/devices/qspi_mtd.c b/drivers/mtd/devices/qspi_mtd.c
index 4731896576a2..a0e3e0671c41 100644
--- a/drivers/mtd/devices/qspi_mtd.c
+++ b/drivers/mtd/devices/qspi_mtd.c
@@ -1289,7 +1289,7 @@ static int qspi_read(struct mtd_info *mtd, loff_t from, size_t len,
                         } else {
-                                        &flash->cmd_info_table[QUAD_IO_READ]);
+                                        &flash->cmd_info_table[DUAL_IO_READ]);
                 } else {

I also changed a line in the programming table, but this may not be absolutely required.

diff --git a/include/linux/mtd/qspi_mtd.h b/include/linux/mtd/qspi_mtd.h
index e33f280f7d4f..71147a85befc 100644
--- a/include/linux/mtd/qspi_mtd.h
+++ b/include/linux/mtd/qspi_mtd.h
@@ -365,11 +365,8 @@ struct qcmdset macronix_porg_cmd_info_table[OPERATION_MAX_LIMIT] = {
                         .bus_width = X1, .dummy_cycles = 0},
                 {.is_ddr = FALSE, .bus_width = X1}
-        /* QUAD_PAGE_PROGRAM */
-        { {.op_code = 0x38, .is_ddr = FALSE, .bus_width = X1, .post_txn = 2},
-                {.address = 0, .is_ddr = FALSE, .len = 3,
-                        .bus_width = X1, .dummy_cycles = 0},
-                {.is_ddr = FALSE, .bus_width = X4}
+        {

Since NVIDIA is already modifying the main Linux kernel, this should definitely be something they should fix up in the sources based on SoM platform hardware or at least include as an option in the DT for QSPI bus width or something along those lines.

Another thing you must be sure is that you have enabled the INPUT on QSPI_SCK_PR0. I learned this the hard way. The Tegra X2 QSPI driver doesn’t work unless the QSPI clock signal has the INPUT enabled. They are probably using a loop-back on the clock internally on the SoC to driver logic.

Thank you very much for your answer! I will test it and inform you if something goes wrong.
It really seems weird to me that the SoM does not allow full 4 data ios QSPI.