QSPI Pinmux Support

I’m trying to configure and use the QSPI connection on the Jetson TX2.

First, is the QSPI controller supported on the Jetson TX2 module using QSPIO_IO0/H7, QSPI_IO1/E8, QSPI_SCK/G8, and QSPI_CS_N/H8?

If so…
When I configure the pinmux spreadsheet as follows:

Pin #    IC Ball Name     SFIO0        Customer Usage       Pin Direction
------------------------------------------------------------------------------
H7       QSPIO_IO0        QSPI_IO0     QSPI_IO0             Output
E8       QSPIO_IO1        QSPI_IO1     QSPI_IO1             Input
G8       QSPI_SCK         QSPI_SCK     QSPI_SCK             Output
H8       QSPI_CS_N        QSPI_CS_N    QSPI_CS_N            Output

And I then use the “Generate DT File” macro and follow that by using the pinmux-dts2cfg.py script to generate the pinmux configuration file using the .dtsi files generated from the pinmux spreadsheet macro, I get the following errors:

ERROR: pin qspi_io0_pr1(0x00000400) field nvidia,enable-input(0x00000040) is not matching, val = 0x00 expected = 0x01
ERROR: pin qspi_io1_pr2(0x00000450) field nvidia,tristate(0x00000010) is not matching, val = 0x01 expected = 0x00

My understanding from the Parker TRM is that IO0 is used for MOSI (output) and IO1 is used for MISO (input). Thus my configuration of the Pin Direction as shown above. However, the mandatory_pinmux.txt file in the following lines:

qspi_io1_pr2:nvidia,function=qspi:nvidia,tristate=<TEGRA_PIN_DISABLE>:nvidia,enable-input=<TEGRA_PIN_ENABLE>:nvidia,lpdr=<TEGRA_PIN_DISABLE>:nvidia,loopback=<TEGRA_PIN_DISABLE>
qspi_io0_pr1:nvidia,function=qspi:nvidia,tristate=<TEGRA_PIN_DISABLE>:nvidia,enable-input=<TEGRA_PIN_ENABLE>:nvidia,lpdr=<TEGRA_PIN_DISABLE>:nvidia,loopback=<TEGRA_PIN_DISABLE>

seems to think what I’m doing with the pin configuration is incorrect. Therefore, have I made a bad assumption/configuration somewhere OR is the mandatory pinmux text file incorrect (should be ignored)?

Looks like latest pinmux spreadsheet can’t set these pin as QSPI SFIO.

Could you try to generate cfg file without using mandatory pinmux file.

Yes. I’ve already done that.

Is the QSPI controller supported on the Jetson TX2 module using QSPIO_IO0/H7, QSPI_IO1/E8, QSPI_SCK/G8, and QSPI_CS_N/H8?

Is the mandatory pinmux text file incorrect?

Yes, we may need to update it.

Hi JDSchroeder,

Have you managed to get the QSPI connected with Jetson TX2 successfully? Any result can be shared?

I’m waiting to hear: Is the QSPI controller supported on the Jetson TX2 module using QSPIO_IO0/H7, QSPI_IO1/E8, QSPI_SCK/G8, and QSPI_CS_N/H8?

Has anyone else successfully used the QSPI connection to the Jetson TX2 module?

We use the following steps the verify read, write and erase .

mtd_debug erase /dev/mtd0 0 0x4000
dd if=/dev/urandom of=/tmp/write bs=16384 count=1
dd if=/tmp/write of=/dev/mtd0 bs=16384 count=1
dd if=/dev/mtd0 of=/tmp/read_after_write.dat bs=16384 count=1
md5sum /tmp/read_after_write.dat /tmp/write