we are developping our own carrier board for AGX Orin and we are looking at the Schematic/layout checklist provided by nvidia. We have two questions about it :
PCI lanes usage
For SSD NVME, 10G Ethernet and USB3, we used the same UPHY as the Jetson AGX Orin devkit:
UPHY4, 5, 10 and 11 for NVME SSD
UPHY6 for 10G ETH
UPHY20 for USB3
However, the checklist schemtics shows other UPHY number for 4 lanes : #C4 interface #C5 interface #C8 interface
Also, the Design Guide recommands #C4 interface for 4lanes PCIe.
Can we stick with the UPHY lanes used on the devkit ? Our guess is yes as it is working on the devkit but it contradicts the Design Guide and the schematics checklist. EDIT : there was a confusion, UPHY0_TX5 is in fact connected to UPHY_TX22. It’s all clear now.
CSI D-PHY
We will use the CSI D-PHY in 4x4 mode (we use 4 radar automotive chips, each having 4 channels) . There are requirements about the max skew for intra-pair and between CLK and DATA
However, there is no requirement about the skew between each group of 4 lanes, hence we think that we don’t need to adjust the length of earch groups of CLK/DATA (we use V4L for data capture). Can you confirm ?
. No skew length matching requirement between lanes, however the skew between DQ and CLK will limit the max allowed difference between them. For the radar auotmotive chip side you will need to refer to the respective data sheet and its limits.
Thank you Sgursal for your answer. I’m sorry, my question wasn’t precise enough.
I was not referring to skew between DQ and DQ of one group that shares the same CLK, but between CLK length of different groups in a 4x4 CSI configuration. In this configuration, there are 4 groups of CLK/DQ1/DQ2/DQ3/DQ4. I suppose that these groups are independent, and no special care should be taken in the length matching of the 4 different CLK lanes, except if there is a mechanism in V4L that requires it. I just wanted to confirm that point with you .
Texas Instruments (vendor of the automotive radar chip) gives requirements for CSI intra-pair and between CLK and DQ, but they say that there is no matching requirement between each CSI group (each group = one radar chip) unless the MCU that reads the data has a specific requirement.
Also, as we are finalizing our custom board, I would like ask you some precisions about the schematic checklist. Can I do that here or should a create a new topic ?
The 4 CSI groups are independent of each other so there is no requirement for clock skew between the groups as such at least from a hardware perspective.
