Question about H.264 of Jonston_TX1

Hello
Everyone at nVIDIA

We have questions about H.264 encoding / decoding behavior of Jonston_TX1.
Q1> Do you use Maxwell_GPU as a hardware resource during H.264 encoding / decoding operation?
Q2> When the answer to Q1 is “Yes”, what percentage is Maxwell_GPU usage when encoding / decoding 1080p / 30fps video?

Also, from the contents of Q & A of the forum for developers, we believe the following contents are correct.

  1. In Jonston_TX 1, it is possible to create multiple H.264 video streams from multiple video inputs.
  2. NVIDIA does not prescribe the upper limit of the combination of the size of the input image and the number of streams. (We want you to specify the limit value)
  3. Jonston_TX 1 is not good at interlaced video.
  4. Connecting to the Jonston_TX1 module The part number of the 400 pin connector to be mounted on the board designed by us is ‘SEAM-50-02.0-S-08-2-A-K-TR’ of Samtec.
    (We are hoping to update the document for developers)

Hi BlueYatagarasu,

Q1> Do you use Maxwell_GPU as a hardware resource during H.264 encoding / decoding operation?
No, besides GPU, TX1 includes hardware-accelerated video codec block.

what percentage is when encoding / decoding 1080p / 30fps video?
Introducing from r24.2.1, we added the Tegra Stats Utility section at L4T documentation, you can check the percentage by use tegrastats:
MSENC is the video hardware encoding engine.
NVDEC is the video hardware decoding engine.

Also, from the contents of Q & A of the forum for developers, we believe the following contents are correct.

  1. In Jonston_TX 1, it is possible to create multiple H.264 video streams from multiple video inputs.
    → Yes, other forum user already can encode 4 channels of 1080p stream with H265 codec, see the post in https://devtalk.nvidia.com/default/topic/920426/jetson-tx1/encode-h265-on-tx1/

  2. NVIDIA does not prescribe the upper limit of the combination of the size of the input image and the number of streams. (We want you to specify the limit value)
    → Please refer to Jetson TX1 Module Data Sheet -
    http://developer.nvidia.com/embedded/dlc/jetson-tx1-module-data-sheet
    External Media

  3. Jonston_TX 1 is not good at interlaced video.
    TX1 HW encoder does not support interlace mode.

  4. Connecting to the Jonston_TX1 module The part number of the 400 pin connector to be mounted on the board designed by us is ‘SEAM-50-02.0-S-08-2-A-K-TR’ of Samtec.
    Yes, you could check section 14 of the Jetson TX1 OEM Product Design Guide which shows the pin orientation. The mating connector P/N from Samtec is shown at the bottom (SEAM-50-02.0-S-08-2-A-K-TR).

Thanks

Hi kayccc

Thank you for your reply.
I will check the specified document.

best regards.

Hi kayccc

It is an additional question.

Q1> Do you use Maxwell_GPU as a hardware resource during H.264 encoding / decoding operation?
Kayccc>No, besides GPU, TX1 includes hardware-accelerated video codec block.

-> In the H.264 / 265 encoding / decoding operation Maxwell_GPU was recognized as unnecessary.

what percentage is when encoding / decoding 1080p / 30fps video?
kayccc>Introducing from r24.2.1, we added the Tegra Stats Utility section at L4T documentation, you can check the percentage by use tegrastats:
MSENC is the video hardware encoding engine.
NVDEC is the video hardware decoding engine.

-> I want to know about CPU load as advance information.
Encoding of H.264 / 1080p / 30 fps When making one stream operation, what percentage of CPU usage is at the recommended operating frequency of Jonston_TX1?

Also, from the contents of Q & A of the forum for developers, we believe the following contents are correct.

  1. In Jonston_TX 1, it is possible to create multiple H.264 video streams from multiple video inputs.
    kayccc> Yes, other forum user already can encode 4 channels of 1080p stream with H265 codec, see the post in https://devtalk.nvidia.com/default/topic/920426/jetson-tx1/encode-h265-on-tx1/

-> Reading the specified thread, I got a new question.
Is not Tegra_X 1 an Octal core? (Looking at the description on the Web, I thought so)
Is it impossible to activate two CPU clusters (A 57 / A 53)?
In actual operation, it is necessary to operate only A57_CPU cluster, and use it as quad core SoC?

  1. NVIDIA does not prescribe the upper limit of the combination of the size of the input image and the number of streams. (We want you to specify the limit value)
    kayccc> Please refer to Jetson TX1 Module Data Sheet -
    http://developer.nvidia.com/embedded/dlc/jetson-tx1-module-data-sheet

→ OK.

  1. Jonston_TX 1 is not good at interlaced video.
    TX1 HW encoder does not support interlace mode.

-> OK.

  1. Connecting to the Jonston_TX1 module The part number of the 400 pin connector to be mounted on the board designed by us is ‘SEAM-50-02.0-S-08-2-A-K-TR’ of Samtec.
    kayccc>Yes, you could check section 14 of the Jetson TX1 OEM Product Design Guide which shows the pin orientation. The mating connector P/N from Samtec is shown at the bottom (SEAM-50-02.0-S-08-2-A-K-TR).

-> We confirmed that it is described in the NOTE column of section 14.0 (P.62) of ‘JetsonTX1_OEM_Product_DesignGuide.pdf’.

Thanks

Hi BlueYatagarasu,

-> In the H.264 / 265 encoding / decoding operation Maxwell_GPU was recognized as unnecessary.
→ Yes.

-> I want to know about CPU load as advance information.
Encoding of H.264 / 1080p / 30 fps When making one stream operation, what percentage of CPU usage is at the recommended operating frequency of Jonston_TX1?
→ The CPU usage is changing dynamically based on the use case different, we don’t have specific data provided.

-> Reading the specified thread, I got a new question.
Is not Tegra_X 1 an Octal core? (Looking at the description on the Web, I thought so)
Is it impossible to activate two CPU clusters (A 57 / A 53)?
In actual operation, it is necessary to operate only A57_CPU cluster, and use it as quad core SoC?
→ TX1 is A57 Quad-core now, please refer to Jetson TX1 Module Data Sheet

Thanks