Hi BlueYatagarasu,
Q1> Do you use Maxwell_GPU as a hardware resource during H.264 encoding / decoding operation?
No, besides GPU, TX1 includes hardware-accelerated video codec block.
what percentage is when encoding / decoding 1080p / 30fps video?
Introducing from r24.2.1, we added the Tegra Stats Utility section at L4T documentation, you can check the percentage by use tegrastats:
MSENC is the video hardware encoding engine.
NVDEC is the video hardware decoding engine.
Also, from the contents of Q & A of the forum for developers, we believe the following contents are correct.
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In Jonston_TX 1, it is possible to create multiple H.264 video streams from multiple video inputs.
→ Yes, other forum user already can encode 4 channels of 1080p stream with H265 codec, see the post in https://devtalk.nvidia.com/default/topic/920426/jetson-tx1/encode-h265-on-tx1/ -
NVIDIA does not prescribe the upper limit of the combination of the size of the input image and the number of streams. (We want you to specify the limit value)
→ Please refer to Jetson TX1 Module Data Sheet -
http://developer.nvidia.com/embedded/dlc/jetson-tx1-module-data-sheet
External Media -
Jonston_TX 1 is not good at interlaced video.
TX1 HW encoder does not support interlace mode. -
Connecting to the Jonston_TX1 module The part number of the 400 pin connector to be mounted on the board designed by us is ‘SEAM-50-02.0-S-08-2-A-K-TR’ of Samtec.
Yes, you could check section 14 of the Jetson TX1 OEM Product Design Guide which shows the pin orientation. The mating connector P/N from Samtec is shown at the bottom (SEAM-50-02.0-S-08-2-A-K-TR).
Thanks