I posted this in another thread but it’s likely to be forgotten there, so moving it to its own question.
Readomg the TX1 SoC Technical Reference Manual version 1.3:
Table 25 describes the pull-up/down function bits of the pad control, but don’t document the actual values of those bits.
Table 29 shows the pinmux control register names, but no bit values.
Is there a register bit mask/map somewhere?
Hi, as said in TRM, “The Tegra X1 devices include many controls for each MPIO pad. Some of these controls can be set on a per-pin basis. Other controls are shared across multiple pins.” The controls in table 25 can be independently configured on a per-pad basis. You can get the specific pad registers setting in doc, e.g. chapter 9.15 lists bit value of some pins.
I don’t understand what you mean by “Table 9.15”
Table 9 is a map of the tertiary interrupt controller.
Table 15 is a map of interrupt controller registers.
The first table in chapter 9 is table 22.
I don’t want the bits of the interrupt controller; I want the bits of the pull-up/down registers.
For example: Both Table 25 and Table 29 define “TRISTATE_CONTROL”
Table 23 also says that each pin has a Tristate_control.
But, there’s no mapping that shows me what bit value that constant has – where do I find the TRISTATE_CONTROL for a particular GPIO pin?
… Oh, I see. What’s called TRISTATE_CONTROL in those three tables, is actually called just TRISTATE in the un-numbered tables in section 9.
So, if I start from the top, and see “TRISTATE_CONTROL,” I have to just guess that, actually, these pins will be called “TRISTATE” in the register map.
I guess I picked a bad example to search for, because PUPD seems to map better between the overview tables and the register bit mask documentation.
Separately, by “Table 9.15” perhaps you meant “the various un-numbered tables found in section 9.15.”
Thanks for the pointer!