Question about TX2 and NX mipi-csi2


Same 1080P30fps MIPI-csi2 4lane yuv422 video,capture video success when connect to TX2 csi-AB port but failed to capture when connect to NX csi-AB port.

Could someone tell me why or how to make NX working with this mipi signal?

I got kernel crash everytime when NX capture the video singal.
kernel-crash.txt (32.4 KB)

trace log with v4l-ctl command:
v4l2-ctl -d /dev/video0 --set-ctrl bypass_mode=1 --stream-mmap --stream-count=1 --stream-to=test.raw --set-fmt-video=width=1920,height=1080,pixelformat=UYVY
trace.txt (203.4 KB)

Really need help.


The trace show the err_intr_type_cil_data_lane_sot_mb_err in the REG NVCSI_PHY_0_CILA_INTR_0_STATUS_CILA_0 not sure if the signal have problem cause this issue.


not sure if the signal have problem cause this issue

I dont think the signal have problem. I use the same SDI-to-CSI2 adapter connect to TX2 and NX, TX2 works fine with this mipi csi signal but NX not. and Why NX crash when I grab video?

Could you please help me to debug this issue. I have no idea to fix this.


I’m still working on this.

Hello ShaneCCC,
TX2 can get video from same signal, the mipi csi2 signal is generated by sdi-to-csi2 adapter, 4-lane, 1920x1080@30p, yuv422,and NX can not.
And I do other test: hdmi-to-mipi adapter signal(4-lane yuv422) connnect to NX csi port AB, can get the video.

Have a try the discontinuous or continuous mode. Also boost the nvcsi/vi clocks to try.

Hi ShaneCCC,

I try discontinuous_clk = “yes” and “no” both, and boost clocks with below cmd:
echo 1 > /sys/kernel/debug/bpmp/debug/clk/vi/mrq_rate_locked
cat /sys/kernel/debug/bpmp/debug/clk/vi/max_rate
echo max_rate > /sys/kernel/debug/bpmp/debug/clk/vi/rate

NX still can not capture mipi csi2 video,generated by LT8918.

Have a try to program the REG NVCSI_PHY_0_CILA_INTR_0_MASK_CILA_0 to mask the error to try.


I closed the topic Kernel crash when capture mipi csi video
and keep this alive to discuss this issue.

I have modify the code to test, and not avoid this NVCSI_PHY_0_CILA_INTR_0_MASK_CILA_0 error.
Could you please show me the patch.

Many thanks.

Have a try to adjust the cil_settletime

I’ve tried set cil_settletime to “0”,“1”,“2” and got the same result.
Does cil_settiletime can be set to any value?

It’s a 8 bit value.

Ok, I’ll modify cil_settletime to try.

The phenomenon is strange.
I have two video adapter, LT6911UXC and LT8918,both of them output mipi csi2 1080P30/60 yuv422 16bit signal.
TX2 csi port AB works fine with both.
NX csi port AB only can capture the video of LT6911UXC and LT8918 alwasy failed.

Hello,What is the standard min/max value should cil_settletime be for 1080@30P?

Min: 85 ns + 6UI
Max:145 ns + 10
“UI Unit Interval, equal to the duration of any HS state on the Clock Lane”
I still dont know how to write cil_settletime = “xxx” in dts file.

Have a check the TRM

Settle time for A0 data lane when moving from LP to HS (LP11->LP01->LP00),
this setting determines how many LP clock cycles (204 MHz lp clock cycles) to wait, after LP00,
before starting to look at the data. 85ns + 6 * UI < (Ths-settle-programmed + 6) * lp clock periods < 145ns +
10 * UI

Hi ShaneCCC,

I’ve tried cil_settletime but still error, and I’m sure that tx2 and nx use the same parameter in dts file.

Hi Suchb,
Did you happen to test with 4K@60 with TX2 when using LT6911UXC? I think which need 8 csi2 lanes. Thanks