Questions about EE3317-A01 x16 PCIe Tx/R


I found that there is a mismatch between Fig 1 Jetson AGX Xavier Root Port Jetson AGX Xavier Endpoint and Fig 3 in the NVIDIA JESTON AGX XAVIER PCIe ENDPOINT DESIGN GUIDLINES as shown below.

For the circled area, I was wondering why we don’t need 0.22uF cap in the real x16 PCIe Tx/Rx swap module.


If you look into schematic of carrier board of dev kit, you will find there are caps on that.

Also please file questions of E3317 in same one topic.

Thanks for the reply and the suggestion. I will do it later.


I have another question about EE3317-A01 x16 PCIe Tx/R module.

I am counting the pcb for the first option(finger-connector) with two layers. And found it seems a bit hard to connect the ground pins for the golden finger. May I ask how many lays have been used for EE3317-A01 x16 PCIe Tx/R module?

Here is my way to route the golden finger, not sure whether it is good or bad(new to PCIe).

Zoomed in version:

It can be seen that the ground connection is a bit messy. Not sure whether I need another layer.

Thank you!

For layout info please refer to guidelines in OEM DG.