Questions about Power Up sequences


We are designing a custom Carrier Board.
I am worried about the power startup timing of the Carrier Board.

So I decided to turn on the Carrier Board 100ms after POWER_EN.
The reason is that the actual measured time from POWER_EN to SYS_RESET was 13ms.
Do you think it is enough to have a 100ms period?

You can refer to the schematic of P3509 board in DLC. SYS_RST is used to control the supply of carrier board directly.

Hi Trumany

Controlling the power of the carrier board with SYS_RST causes inconvenience.
Because it uses SYS_RESET for the RESET pin of some ICs on the carrier board.
This is an improper sequence in which the power turns on after the RESET is released.


I don’t get what you mean. The carrier supplies should be ON after RESET released. So using RESET to control the carrier supplies has no problem.

I’m sorry I wasn’t good at explaining.
Of course, it’s okay to control the carrier board’s power supply with SYS_RST,
However, it is not possible to reset the peripheral IC with SYS_RST.
The power sequence of most ICs in the world is RESET release after power on.

The figure below is for reference .

It depends on your design. If you are sure about the timing (100ms?) from POWER_EN to carrier power rails on is enough for module power on, then you can implement the delay to your design.

thank you.

POWER_EN after releasing SYS_RES, changed the RESET of peripheral to POR.
I managed to follow the power sequence rules.

I would like JETSON to output PMIC_PG in the future.


If my understanding to your question is correct: as you can see, SYS_RESET is used to the EN of carrier power supply not the RESET of the chip. So it needs to add delay design between carrier power supply and the RESET of chip on carrier.

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