hi：
i have bring up gmsl max96712 + four max9295, yuv 16 bit 3840*2160 sensor,
After the driver is loaded, the first open display is normal, and the second re-open display is abnormal，now upload our hardware design，and the ok log,and no ok log
sg4a.log (227.2 KB)
sg4a-no.log (234.9 KB)
It could be the GMSL chip didn’t reset well cause the problem.
Thanks
hi:
about another topic：
R35.3.1 AGX orin bring up imx728 set serdes_pix_clk_hz to 600M ，Preview black screen - Jetson & Embedded Systems / Jetson AGX Orin - NVIDIA Developer Forums
this have release the patch？
what cause the problem?
The fix will release next release that coming soon.
Thanks
hi：
Is there any patch released first, and verify whether it works well first
No, the J5.1.2 should be coming soon.
hi：
I want to know what causes it
OK, looks like your problem is different with the topic about imx728 due to your sensor is YUV sensor instead of bayer sensor and the APP is different too.
Please verify your sensor HW and driver by v4l2-ctl like below command.
v4l2-ctl --stream-mmap
hi：
We’re talking about a different topic,
R35.3.1 AGX orin bring up imx728 set serdes_pix_clk_hz to 600M ，Preview black screen - Jetson & Embedded Systems / Jetson AGX Orin - NVIDIA Developer Forums
I want to know what causes it，the J5.1.2 can you make sure it’s fixed？
It’s fixed for that case in next release.
Thanks
hi:
Wait for your new version，thanks.
Now we discuss current topics,i will do the following verification for this problem, and change serdes_pix_clk_hz to 300000000, which is no problem in the test verification. Now we want to connect two 8MP sensors, so we need to change serdes_pix_clk_hz to 600000000. The corresponding gmsl deserializer clk is modified to 2.4Gbps, so it is not possible to test again. I think this problem is the same as the previous problem we discussed. After serdes_pix_clk_hz is increased, Let’s go to gst-launch-1.0 v4l2src device=/dev/video0! The xvimagesink -ev preview command is not displayed with a black screen
Do you mean unable run two cameras simultaneously?
hi:
Do you mean unable run two cameras simultaneously?—>yes,because two cameras will affect serdes_pix_clk_hz to rise to 600000000，and deserializer lane rate reg set 0x37,In this case, the preview screen will be black
mclk_khz = “24000”;
num_lanes = “4”;
tegra_sinterface = “serial_a”;
vc_id = “0”;
discontinuous_clk = “no”;
dpcm_enable = “false”;
cil_settletime = “0”;
dynamic_pixel_bit_depth = “16”;
csi_pixel_bit_depth = “16”;
mode_type = “yuv”;
pixel_phase = “uyvy”;
active_w = "3840";
active_h = "2160";
readout_orientation = "0";
line_length = "4200";
inherent_gain = "1";
pix_clk_hz = "248832000";
serdes_pix_clk_hz = "300000000";
now serdes_pix_clk_hz set 300M，and max96712 lane rate set 0x2c, in this case, tesk ok,but only connect one sensor.
Set the serdes clock to 300000000 for two cameras and boost the clocks to try.
sudo su
echo 1 > /sys/kernel/debug/bpmp/debug/clk/vi/mrq_rate_locked
echo 1 > /sys/kernel/debug/bpmp/debug/clk/isp/mrq_rate_locked
echo 1 > /sys/kernel/debug/bpmp/debug/clk/nvcsi/mrq_rate_locked
echo 1 > /sys/kernel/debug/bpmp/debug/clk/emc/mrq_rate_locked
cat /sys/kernel/debug/bpmp/debug/clk/vi/max_rate |tee /sys/kernel/debug/bpmp/debug/clk/vi/rate
cat /sys/kernel/debug/bpmp/debug/clk/isp/max_rate | tee /sys/kernel/debug/bpmp/debug/clk/isp/rate
cat /sys/kernel/debug/bpmp/debug/clk/nvcsi/max_rate | tee /sys/kernel/debug/bpmp/debug/clk/nvcsi/rate
cat /sys/kernel/debug/bpmp/debug/clk/emc/max_rate | tee /sys/kernel/debug/bpmp/debug/clk/emc/rate
hi:
Set the serdes clock to 300000000 for two cameras and boost the clocks to try.----》yes，test ok，
So how do you integrate this into your code and load it
Does both cameras working without boost the clocks by setting serdes to 300000000?
What’s the configure in the tegra-camera-platform{}?
num_csi_lanes = <4>;
max_lane_speed = <1500000>;
min_bits_per_pixel = <10>;
vi_peak_byte_per_pixel = <2>;
vi_bw_margin_pct = <25>;
max_pixel_rate = <240000>;
isp_peak_byte_per_pixel = <5>;
isp_bw_margin_pct = <25>;
hi:
Does both cameras working without boost the clocks by setting serdes to 300000000? → max96712 rate set 0x37, and the serdes_pix_clk_hz set 300M
now i configure in the tegra-camera-platform
tegra-camera-platform {
compatible = “nvidia, tegra-camera-platform”;
num_csi_lanes = <4>;
max_lane_speed = <1500000>;
min_bits_per_pixel = <10>;
vi_peak_byte_per_pixel = <2>;
vi_bw_margin_pct = <25>;
isp_peak_byte_per_pixel = <5>;
isp_bw_margin_pct = <25>;
max_pixel_rate = <750000>;
So it’s working well while set serdes to 300000000?
I would suggest this configure and set num_lanes to 12 to acquire more bandwidth.
hi:
Does both cameras working without boost the clocks by setting serdes to 300000000? ----->
setting serdes to 300000000 I don’t know how to set it. What I know at present is that the lane rate of the destringer is 2.3Gbps, because there are two camera，
You mean that this property serdes_pix_clk_hz is set to 300000000，now set serdes_pix_clk_hz to 300000000, and boost the clocks, it’s working well
echo 1 > /sys/kernel/debug/bpmp/debug/clk/vi/mrq_rate_locked
echo 1 > /sys/kernel/debug/bpmp/debug/clk/isp/mrq_rate_locked
echo 1 > /sys/kernel/debug/bpmp/debug/clk/nvcsi/mrq_rate_locked
echo 1 > /sys/kernel/debug/bpmp/debug/clk/emc/mrq_rate_locked
