Reading BR_CID from kernel

[_Becu]

Hello,

Basically the same question from this topic, but on an Orin NX on JP 5.1.2. We want to link the BR_CID read while in recovery mode to a value that can be read from kernel.

Saw that ecid doesn’t exist anymore in /proc/device-tree/chosen.

Tried reading with nv_fuse_read and from /sys/devices/platform/tegra-fuse/ecid and we get the same value, but it doesn’t seem related to the BR_CID from tegrarcmv2

Thanks!

[KevinFFF]

Hi _Becu,

@_Becu

Basically the same question from this topic,

That is from R32.X and it would not work for R35.X.

Please apply the following patch and reflash the board first.

--- a/drivers/soc/tegra/fuse/fuse-burn.c
+++ b/drivers/soc/tegra/fuse/fuse-burn.c
@@ -61,6 +61,26 @@
 
 #define TEGRA_FUSE_SHUTDOWN_LIMIT_MODIFIER	2000
 
+#define FUSE_OPT_LOT_CODE_1_MASK 0xfffffff
+#define FUSE_OPT_OPS_RESERVED 0x120
+#define FUSE_OPT_OPS_RESERVED_MASK 0x3F
+#define ECID_ECID0_0_RSVD1_MASK                0x3F
+#define ECID_ECID0_0_Y_MASK            0x1FF
+#define ECID_ECID0_0_Y_RANGE           6
+#define ECID_ECID0_0_X_MASK            0x1FF
+#define ECID_ECID0_0_X_RANGE           15
+#define ECID_ECID0_0_WAFER_MASK                0x3F
+#define ECID_ECID0_0_WAFER_RANGE       24
+#define ECID_ECID0_0_LOT1_MASK         0x3
+#define ECID_ECID0_0_LOT1_RANGE                30
+#define ECID_ECID1_0_LOT1_MASK         0x3FFFFFF
+#define ECID_ECID1_0_LOT0_MASK         0x3F
+#define ECID_ECID1_0_LOT0_RANGE                26
+#define ECID_ECID2_0_LOT0_MASK         0x3FFFFFF
+#define ECID_ECID2_0_FAB_MASK          0x3F
+#define ECID_ECID2_0_FAB_RANGE         26
+#define ECID_ECID3_0_VENDOR_MASK       0xF
+
 struct fuse_burn_data {
 	char *name;
 	u32 start_offset;
@@ -787,7 +807,68 @@ static unsigned long long tegra_chip_uid(void)
 static ssize_t tegra_fuse_read_ecid(struct device *dev,
 		struct device_attribute *attr, char *buf)
 {
-	sprintf(buf, "%llu\n", tegra_chip_uid());
+	u32 reg;
+	u32 vendor;
+	u32 fab;
+	u32 lot0;
+	u32 lot1;
+	u32 wafer;
+	u32 x;
+	u32 y;
+	u32 rsvd1;
+	u32 ecid[4];
+
+	tegra_fuse_readl(FUSE_OPT_VENDOR_CODE, &reg);
+	vendor = reg & FUSE_OPT_VENDOR_CODE_MASK;
+
+	tegra_fuse_readl(FUSE_OPT_FAB_CODE, &reg);
+	fab = reg & FUSE_OPT_FAB_CODE_MASK;
+
+	tegra_fuse_readl(FUSE_OPT_LOT_CODE_0, &reg);
+	lot0 = reg;
+
+	tegra_fuse_readl(FUSE_OPT_LOT_CODE_1, &reg);
+	lot1 = reg & FUSE_OPT_LOT_CODE_1_MASK;
+
+	tegra_fuse_readl(FUSE_OPT_WAFER_ID, &reg);
+	wafer = reg & FUSE_OPT_WAFER_ID_MASK;
+
+	tegra_fuse_readl(FUSE_OPT_X_COORDINATE, &reg);
+	x = reg & FUSE_OPT_X_COORDINATE_MASK;
+
+	tegra_fuse_readl(FUSE_OPT_Y_COORDINATE, &reg);
+	y = reg & FUSE_OPT_Y_COORDINATE_MASK;
+
+	tegra_fuse_readl(FUSE_OPT_OPS_RESERVED, &reg);
+	rsvd1 = reg & FUSE_OPT_OPS_RESERVED_MASK;
+
+	reg = 0;
+	reg |= rsvd1 && ECID_ECID0_0_RSVD1_MASK;
+	reg |= (y & ECID_ECID0_0_Y_MASK) << ECID_ECID0_0_Y_RANGE;
+	reg |= (x & ECID_ECID0_0_X_MASK) << ECID_ECID0_0_X_RANGE;
+	reg |= (wafer & ECID_ECID0_0_WAFER_MASK) << ECID_ECID0_0_WAFER_RANGE;
+	reg |= (lot1 & ECID_ECID0_0_LOT1_MASK) << ECID_ECID0_0_LOT1_RANGE;
+	ecid[0] = reg;
+
+	lot1 >>= 2;
+
+	reg = 0;
+	reg |= lot1 & ECID_ECID1_0_LOT1_MASK;
+	reg |= (lot0 & ECID_ECID1_0_LOT0_MASK) << ECID_ECID1_0_LOT0_RANGE;
+	ecid[1] = reg;
+
+	lot0 >>= 6;
+
+	reg = 0;
+	reg |= lot0 & ECID_ECID2_0_LOT0_MASK;
+	reg |= (fab & ECID_ECID2_0_FAB_MASK) << ECID_ECID2_0_FAB_RANGE;
+	ecid[2] = reg;
+
+	reg = 0;
+	reg |= vendor & ECID_ECID3_0_VENDOR_MASK;
+	ecid[3] = reg;
+
+	sprintf(buf, "%08x%08x%08x%08x\n", ecid[3], ecid[2], ecid[1], ecid[0]);
 	return strlen(buf);
 }
 #endif

and run the following command to read ecid.

# cat /sys/devices/platform/efuse-burn/ecid

[_Becu]

Hi @KevinFFF,

Tried with the patch, rebuild and reflash, but it seems the value is unchanged (only ~24 bits match between them).

[KevinFFF]

Could you help to share the result of the following 2 conditions?

1. In force recovery state, run the following command on your host:

$ ./tegrarcm_v2 --new_session --chip 0x23 0 --uid

2. After the patch applied, run the following command on your board

# cat /sys/devices/platform/efuse-burn/ecid

[_Becu]

Sure

BR_CID is 0xA9012344705DD2CB780000000AFF81C0
ecid as read from /sys/devices/platform/efuse-burn/ecid (and some other places i’ve found it) is 9543798680149818887

[KevinFFF]

@_Becu

ecid as read from /sys/devices/platform/efuse-burn/ecid (and some other places i’ve found it) is 9543798680149818887

Do you read this value after applying the patch I shared in 27/Oct.?

[_Becu]

It works now, the last 25 characters match. Thank you for the help!

Didn’t see that there’s more than just the defines, there’s no scroll bar :D