REG: TX2 EVAL BOARD CVM CONNECTOR

hi,
I’m designing a custom carrier board with TX2 module, i have noticed that the CVM CONNECTOR used in the EVAL board ( 400 pin connector ), the solder paste area was provided 0.25mils greater than pin area and the solder mask has been provided 0.16mils lesser than solder paste.
can anyone help me on this?
will this create any issue on PCB assembly phase, since solder mask area is lesser than that of solder paste area?

thanks

Hi, please refer to this topic: https://devtalk.nvidia.com/default/topic/1026382