Regarding hard float toolchain for NVIDIA TX2

Hi All,

   I need information on hard float tool chain (Ex: arm-linux-gnueabihf-g++), to compile the code on NVIDIA Jetson TX2. Please provide me the information on this, as this is very helpful in compiling the code with lot of floating point operations.

Thanks & Regards
Shalini KP


We don’t have too much experience with hard float tool chain.

But arm-linux-gnueabihf-g++ can be installed with this command:

sudo apt-get install g++-arm-linux-gnueabi

FYI, armhf is for 32-bit ARMv7 with hard float calling convention. Although a TX2 has a compatibility mode for 32-bit it is natively 64-bit. The only way 32-bit would work is if you install 32-bit linker and compatibility library support. If you want to target output on a TX2 for native use it is arm64/aarch64.

What’s wrong with the G++ that comes by default on the Jetson? It does hardware floating point anyway.
“hard floating point” is only needed for low-end Cortex M4 chips when they have an FPU, and for old Raspberry Pis that bolted FPU onto ARM-6.

Just “apt install g++” and you’re good to go!

nvidia@tegra-ubuntu:/tmp$ cat > foo.cpp
#include <stdio.h>

float fun(float a, float b) {
  return a / b;


nvidia@tegra-ubuntu:/tmp$ gcc -c foo.cpp 
nvidia@tegra-ubuntu:/tmp$ objdump --disassemble foo.o

foo.o:     file format elf64-littleaarch64

Disassembly of section .text:

0000000000000000 <_Z3funff>:
   0:	d10043ff 	sub	sp, sp, #0x10
   4:	bd000fe0 	str	s0, [sp,#12]
   8:	bd000be1 	str	s1, [sp,#8]
   c:	bd400fe1 	ldr	s1, [sp,#12]
  10:	bd400be0 	ldr	s0, [sp,#8]
  14:	1e201820 	fdiv	s0, s1, s0
  18:	910043ff 	add	sp, sp, #0x10
  1c:	d65f03c0 	ret

Note the “fdiv.”