Request rtcpu debug firmware for Jetpack 6.2

Robotics & Edge Computing Jetson & Embedded Systems Jetson Orin Nano
1

platform is Jetson Orin Nano Super

5

Hi support,

we are developing a video product with Jetson orin nano devkit super module, and we have encountered some problems .

  • The error massage listed as follow:
[Error]:
uncorr_err: request timed out after 2500ms
err_rec: successfully reset to the capture channel 
...
  • Our hardware design information is:
RGB sensor-> ISP->MAX9295D-MAX96724->Jetson orin nano devkit super CSI0/CSI1

RGB sensor output format is RAW10,2lane
ISP  output format is YUV422-8bit 2lane
MAX96724 output format is YUV422-8bit 2lane@1.5Gbps/per lane

and our carrier board is not customized.

  • Our test pipeline is
v4l2-ctl -d /dev/video0 --set-fmt-video=width=1920,height=1080,pixelformat="UYVY" --set-ctrl bypass_mode=0 --stream-mmap --stream-count=1000 --stream-to=/dev/null --verbose
  • Our Jetpack Version: 6.2 with Jetson_Linux_R36.4.3_aarch64

We are searching a lot of posts from the forums and we have already read NVIDIA Jetson Linux Developer Guide,and we have tried some advices from those posts, unfortunately, we still faced this problem.

So ,we attempt to request rtcpu debug firmware to get more debug info from NVIDIA Jetson’s VI/NVCSI.

thanks.

Here there’re some actions we have done for your information:

  1. DTS file:
    tegra234-p3737-camera-sc2310-overlay.txt (6.6 KB)

  2. MIPI
    we have already probed the mipi signal and they comply with MIPI specifications.

  3. boost clk
    Nothing happened

  4. enable ftrace

        v4l2-ctl-4487    [001] .......  3519.430839: tegra_channel_capture_setup: vnc_id 0 W 1920 H 1080 fmt 13
        v4l2-ctl-4487    [001] .......  3519.431194: tegra_channel_set_stream: enable : 0x1
 vi-output, z_ov-4488    [000] .......  3519.431235: vi_task_submit: class_id:48 ch:0 syncpt_id:26 syncpt_thresh:0 pid:4488 tid:4488
 vi-output, z_ov-4488    [000] .......  3519.431250: vi_task_submit: class_id:48 ch:0 syncpt_id:26 syncpt_thresh:0 pid:4488 tid:4488
 vi-output, z_ov-4488    [000] .......  3519.431251: vi_task_submit: class_id:48 ch:0 syncpt_id:26 syncpt_thresh:0 pid:4488 tid:4488
 vi-output, z_ov-4488    [000] .......  3519.431253: vi_task_submit: class_id:48 ch:0 syncpt_id:26 syncpt_thresh:0 pid:4488 tid:4488
        v4l2-ctl-4487    [001] .......  3519.432036: tegra_channel_set_stream: 13e00000.host1x:nvcsi@15a00000- : 0x1
        v4l2-ctl-4487    [001] .......  3519.432038: csi_s_stream: enable : 0x1
        v4l2-ctl-4487    [001] .......  3519.432424: tegra_channel_set_stream: sc2310_9295d 9-001b : 0x1
     kworker/0:1-45      [000] .......  3519.488263: rtcpu_vinotify_event: tstamp:110773697462 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:3544753280928 data:0x799d580010000000
     kworker/0:1-45      [000] .......  3519.488266: rtcpu_vinotify_event: tstamp:110773697720 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:3544753290592 data:0x0000000031000001
     kworker/0:1-45      [000] .......  3519.488266: rtcpu_vinotify_event: tstamp:110773697941 cch:0 vi:0 tag:VIFALC_ACTIONLST channel:0x23 frame:0 vi_tstamp:3544753295136 data:0x0000000007020001
     kworker/0:1-45      [000] .......  3519.488267: rtcpu_vinotify_event: tstamp:110773698191 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:3544753389152 data:0x799d550010000000
     kworker/0:1-45      [000] .......  3519.488268: rtcpu_vinotify_event: tstamp:110773698406 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:3544753398944 data:0x0000000031000002
  1. v4l2_ctl -c override_capture_timeout=-1
    Nothing happened
6

hello harveyrou,

you may see-also Topic 326038 for JetPack-6.2/l4t-r36.4.3 camera firmware with debug flag enabled.

7

Hi JerryChang,

thank you for your kindly reply.

replace the camera debug firmware steps

Step 4 is fail, when I use this command below

sudo ./flash.sh --no-flash -r -k A_rce-fw jetson-orin-nano-devkit-super nvme0p1

and the error message is:

sudo ./flash.sh  --no-flash -r -k A_rce-fw jetson-orin-nano-devkit-super nvme0p1

###############################################################################
# L4T BSP Information:
# R36 , REVISION: 4.3
# User release: 0.0
###############################################################################
ECID is 
Board ID() version() sku() revision()
Preset RAMCODE is 
Chip SKU(00:00:00:D3) ramcode() fuselevel(fuselevel_production) board_FAB()
emc_opt_disable_fuse:(0)
Error: Unrecognized module SKU

also, I have run another command

sudo ./tools/kernel_flash/l4t_initrd_flash.sh --no-flash  -k A_rce-fw jetson-orin-nano-devkit-super nvme0p1
Please install the Secureboot package to use initrd flash for fused board
/home/nvidia/jetson/Linux_for_Tegra/tools/kernel_flash/l4t_initrd_flash_internal.sh --no-flash --no-flash -k A_rce-fw jetson-orin-nano-devkit-super nvme0p1
************************************
*                                  *
*  Step 1: Generate flash packages *
*                                  *
************************************
Create folder to store images to flash
Generate image for internal storage devices
Generate images to be flashed
ADDITIONAL_DTB_OVERLAY=""  /home/nvidia/jetson/Linux_for_Tegra/flash.sh --no-flash --sign -k "A_rce-fw"  jetson-orin-nano-devkit-super nvme0p1

###############################################################################
# L4T BSP Information:
# R36 , REVISION: 4.3
# User release: 0.0
###############################################################################
ECID is 
Board ID() version() sku() revision()
Preset RAMCODE is 
Chip SKU(00:00:00:D3) ramcode() fuselevel(fuselevel_production) board_FAB()
emc_opt_disable_fuse:(0)
Error: Unrecognized module SKU 
Error: failed to generate images
Cleaning up...

How can i fix this issue?

8

hello harveyrou,

please update your target board to AGX Orin,
it’s running flash script to generate signed/encrypted rce-fw.
for instance,
$ sudo ./flash.sh --no-flash -r -k A_rce-fw jetson-agx-orin-devkit mmcblk0p1

9

Hi JerryChang,

It seems to upgrade A_rce successful, Thank you so much!

[   69.690788] [RCE] tegra_nvcsi_stream_set_config(vm0, stream=1, csi=1)
[   69.690793] [RCE] MIPI clock = 1500000 kHz, tHS-SETTLE = 0, tCLK-SETTLE = 0
[   69.690796] [RCE] ===== NVCSI Stream Configuration =====
[   69.690798] [RCE] stream_id: PP 1, csi_port: PORT B
[   69.690801] [RCE] Brick: PHY 0, Mode: D-PHY
[   69.690804] [RCE] Partition: CIL B, LP bypass: Enabled, Lanes: 2
[   69.690806] [RCE] Clock information:
[   69.690808] [RCE] MIPI clock rate: 1500.00 MHz
[   69.690811] [RCE] T_HS settle: 0, T_CLK settle: 0
[   69.690813] [RCE] ======================================
[   69.690816] [RCE] tegra_nvcsi_stream_open(vm0, stream=1, csi=1)
[   69.690818] [RCE] nvcsi_reset_data_lanes: NVCSI_PHY_0_NVCSI_CIL_A_SW_RESET_0 = 00000000
[   69.690821] [RCE] nvcsi_reset_data_lanes: NVCSI_PHY_0_NVCSI_CIL_B_SW_RESET_0 = 00000003
[   69.690823] [RCE] nvcsi_reset_lane_merger: NVCSI_PHY_0_LM_SW_RESET_0 = 00000002
[   69.690826] [RCE] nvcsi_task_function: NVCSI_REINIT_SETUP_TYPE++
[   69.690828] [RCE] nvcsi_task_function: NVCSI_REINIT_SETUP_TYPE--
[   69.690830] [RCE] nvcsi_reset_lane_merger: NVCSI_PHY_0_LM_SW_RESET_0 = 00000000
[   69.690832] [RCE] nvcsi_calc_ths_settle ths_settle 22
[   69.690835] [RCE] nvcsi_calc_ths_settle ths_settle 22
[   69.690837] [RCE] nvcsi_calc_tclk_settle tclk_settle 35
[   69.690839] [RCE] nvcsi_reset_data_lanes: NVCSI_PHY_0_NVCSI_CIL_A_SW_RESET_0 = 00000000
[   69.690841] [RCE] nvcsi_reset_data_lanes: NVCSI_PHY_0_NVCSI_CIL_B_SW_RESET_0 = 00000000
[   69.690844] [RCE] nvcsi_task_function: NVCSI_DPHY_SETUP_MSG++
[   69.690846] [RCE] nvcsi_task_function: NVCSI_DPHY_SETUP_MSG--
[   69.690848] [RCE] Deskew setup message sent for port 1 num_lane 2
[   69.690850] [RCE] nvcsi_enable_deskew: Line(3256)
[   69.690853] [RCE] nvcsi_enable_deskew: Line(3286)
[   69.690855] [RCE] nvcsi_enable_deskew: Line(3317)
[   69.690857] [RCE] nvcsi_stream_enable: enable pixel parser++ Line(3554)
[   69.690859] [RCE] nvcsi_stream_enable: enable pixel parser-- Line(3591)