Is there a required time delay between asserting POWER_BTN_N (L61) and MODULE_POWER_ON (L54) of the Jetson Xavier AGX at both power on and off? Can both pins be tied to the same power-sequence logic without time delay?
Required time delay between asserting POWER_BTN_N (L61) and MODULE_POWER_ON (L54) of the Jetson Xavier AGX
There is request (not so critical) as listed in power on sequence in OEM DG. L54 should be asserted later than L61 and vin_pwr_bad, and after HV and MV are stable.
How much time delay are we typically looking at between L61 and L54? Is 100 ms sufficient?
Can L55 and L61 be tied to same logic if we are not looing to do physical power-button turn-on?
It depends on your design. The key point is module_power_on should after HV, MV are stable and vin_pwr_bad is deserted no matter what the delay is if you are not using physical button.
Thanks for the clarification.
This is our proposed power-on sequence. Let me know if there is no risk in the following.
- Provide HV, MV (no delay in between the 2).
- De-assert vin_pwr_bad when both HV and MV reaches beyond UVLO (or PGood)
- Enable module_power_on (L54) and POWER_BTN_N (L61) with no delay in between L54 and 61.
Seems no problem in theory, but we can’t guarantee it can work without risk as it is not validated on devkit. What we can suggest is to follow the power-on/off sequence in design guide well.